Daisy chaining FPGA with CPLDs

CPLDs aren't typically configured like FPGAs. When the FPGA is changed, there's usually an update to the image either in a programming ROM or in system flash. In the same way when a CPLD is changed, the ROM in the CPLD is updated. These updates are typically a different process than the configuration chaining you're reading about.

JTAG chains can configure *and* update and are designed to be daisy-chained. On programming cable can perform CPLD updates, FPGA updates if you're using the programming ROM, and on-the-fly CPLD configurations for testing new FPGA code with a volatile configuration.

Yes, you can chain as many JTAG-compliant devices as you like in a JTAG chain. For example, you could chain a CPLD, an FPGA and the configuration PROM for the FPGA. No problem.

From an electrical and JTAG spec perspective you are correct.

But the software that you use must either directly supports all of the devices in the chain or allow for some form of bypassing 'foreign' devices in that chain. It's not really a 'JTAG issue' at that point, but more of a tool support issue. Consider a single JTAG chain consisting of devices from Actel, Altera, Lattice and Xilinx. JTAG download software from any of the vendors will only work if they allow those 'other' devices to be bypassed while you're working with one particular vendor's part. Whether that can happen or not simply needs to be investigated with the JTAG software tool. Alternatively, one could use JTAG software from a neutral party (such as Asset-Intertech and several others) to get at all of the parts. There are tradeoffs to that approach as well, but again something to investigate.

There are also some devices that really want to be 'first' in the chain. So far I've only run into this as an issue with certain processors that use JTAG as the interface for software code debug but the problem is that the JTAG software assumed that the processor was the first and only device in the JTAG chain and flat out didn't work if it wasn't. It wasn't a JTAG hardware issue, it was the software that the vendor supplied but if you need to use the software to debug code (and yes you do) then you need to use that vendor's tool. Programming/verifying CPLDs is somewhat more amenable to other solutions but just another example of how the software that will be used is really the determining criteria for how you lay out the JTAG chain.

KJ

One little note: pay attention to differing JTAG voltage levels...

Peter Wallace