D-Type Flip flop with negated Q in Webise for a schematic capture

Sorry for the naive question, but how do I capture a schematic with a D and J-K FF that do have negated Q? I tried to draw the schematic with WebISE 13.3 and there is not such a thing readily available. TIA.

Giuseppe Marullo

Reply to
Giuseppe Marullo
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You might be more likely to get an answer if you post this question at the Xilinx forums, for example:

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Reply to
RCIngham

Use an inverter on the clock net. It will get absorbed into the FFs.

Andy

Reply to
Andy

Hi,

Giuseppe Marullo skrev 2011-12-12 10:32:

When you run P&R the optimizing will reduce your design whenever possible. Check the output of the build process and see what it says.

Or make a very tiny design then you can see in fpga_editor what the P&R did do.

/michael

Reply to
Michael Laajanen

The OP asked for a "negated Q", which I would interpert as being an invertor on the Q output and not on the CLK input.

Ed McGettigan

-- Xilinx Inc.

Reply to
Ed McGettigan

(snip, someone wrote)

In any case, the inverter should be absorbed where possible, and included elsewhere.

In the TTL days, it was usual for FF's to have Q and Qbar outputs, with no extra inverter delay in the Qbar case.

But even more, the OP didn't ask about the logic, but how to draw it. (Even though I don't especially like schematic capture.)

I suppose the schematic capture tools could add a Qbar output and generate an inverter. Maybe they allow for inverting outputs by adding circles. It is a tools question, not a logic question.

-- glen

Reply to
glen herrmannsfeldt

Glen, exactly. I need to do the capture thing because it is not so trivial to convert the schematic into verilog at first glance, and the FF uses both Q and Qbar. I was thinking it was a fault from my understanding of the tool, but qbar are missing on all FF i found in the tool.

The other way would it be to write a custom block where inside a verilog would implement the desired FF but maybe there is a simpler way.

Giuseppe Marullo

Reply to
Giuseppe Marullo

Touche! I have posted the same question there.

Reply to
Giuseppe Marullo

If you are going to be using schematic entry, then it is quite easy to build all the primitives you need out of simpler primitives and make a custom library of them. I still do this on some CPLD interface projects where simple definitions in schematic form are more concise. I build N-way tristate buffers and tristate FFs and such that way.

Jon

Reply to
Jon Elson

Personally, I think I can write verilog faster than I can get the lines drawn for schematic capture, but others may be different.

For FPGAs, inverters will usually be moved into the logic before or after, changing bits in the appropriate LUT. So no delay difference.

That wasn't true in TTL. So, now the reason for them is gone, and the tools don't support them.

On some, you can draw your own symbol, including the circles.

-- glen

Reply to
glen herrmannsfeldt

If it can be drawn in a schematic in can be written in Verilog and probably written faster than it can be drawn.

always @ (posedge clk) begin q

Reply to
Ed McGettigan

To be true to the original, you should have written:

always @ (posedge clk) begin q you need Qbar then just take Q and invert it (Qbar=!Q) and then apply

Note that placing the inverter before or after the flip-flop can make a difference if it actually means adding a LUT to do the inversion, and also note that given the freedom the synthesis tools can move the LUT before or after the flip-flop to help meet timing (register balancing enabled). So regardless of how you enter the code, the result after synthesis and map can vary. Don't think that just because you're entering schematics that the actual implementation will match your schematic. At least for FPGA's, ISE treats schematic entry just like structural HDL and will do all of the same optimizations. From ISE you should also have the option to view the "technology schematic" after translation to see what became of your "inverter".

I personally like schematic entry but detest Xilinx's implementation of it, so I haven't used it since they dropped the Aldec front-end tools after Foundation 4.1i. In those days if I didn't see the symbol I needed, I'd write Abel code and create a symbol from it. With the newer ISE, you can also use Verilog of VHDL to enter blocks, and then create a schematic symbol from the HDL. Or as suggested you can create hierarchical symbols with the schematic editor. There are many ways to skin a cat...

-- Gabor

Reply to
Gabor

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Gabor,

Your code would generate two registers one for q and one for qbar. IMHO, this is further removed from the original intent and would use more resource than an inversion that would likely be merged into the next LUT or register input.

Ed McGettigan

-- Xilinx Inc.

Reply to
Ed McGettigan

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I'm pretty sure most tools are smart enough to understand that the one description is equivalent to the other and optimize the code to a single register and shove the inversion into the following logic, assuming there is any. Am I wrong about this?

I know I have seen equivalent registers combined into one when I was trying to reduce the fan out on a net.

Rick

Reply to
rickman

(snip)

always @(posedge clk) begin q = #1 d; qbar = #1 !d; end

(snip)

The tools are very good at removing duplicate register. Even from different modules at different nesting levels, they will still be removed, such that only one is used. (There is a message when it does it.)

It might even be that a single register can be duplicated to help meet the timing requirements, though I don't remember seeing it do that.

-- glen

Reply to
glen herrmannsfeldt

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My preference is to write code that will match the synthesised logic. I don't see the benefit in writing code for two registers with the assumption that the synthesizer will remove one of them and leave the other. Ok, the same could be said about the inverter being absorbed in the next stage, but for me it is easier to rationalize a function optimization than the removal of a sequential storage element and it's less coding and I think easier to understand when looking at simulation waveforms.

I think that this has been beaten to death now. Either way will generate logical equivalent results.

Ed McGettigan

-- Xilinx Inc.

Reply to
Ed McGettigan

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