We have developed data acquisition system which uses Cypress FX2 as the USB
2.0 interface. State machine for control and conversion of data between AD converters and FX2 is implemented using Xilinx Spartan 2 FPGA. The problem is that with higher data rates (up to 25 Mbit/s) we experience FX2 internal FIFO stalls and missing data on the receiving side. Small FIFO implemented inside FPGA does not help to resolve the problem. On the PC, data acquisition is implemented using CyAPI & CyUSB. USB bulk mode is used for transfer.As mentioned data rate is only a fraction of USB 2.0 bandwidth, I don't know if the mentioned problem is related to the implementation of the receiver side (CyAPI) or lacking capability to sustain such bandwidth within Cypress FX2.
Did anyone have similar problems using FX2 and how you manage to solve it?
I will appreciate any help to resolve this problem, if possible in software - hardware solution will require redesign of the PCB and implementation/addition of large size FIFO to buffer FX2 stalls (which may, according to our experience, extend up to 50 ms).
Thanks,
Damir