Hi,
I try to implement a DDR3 hard memory controller in a Cyclone v device a 5CGXFC3B6F23C7.
I created an DDR3 hard memory controller IP core with the Megawizard, integrated the core in my design and added my design files in Quartus.
The fitter of Quartus gives following error message
Error (15332): Port SHIFTEN of cyclonev_pll_reconfig "HeadTop:I_HeadTop|DDR3Controller:I_MemCtrlBlk|Ddr3MemCtrl:Ddr3MemCtrl_1|Ddr3MemCtrl_000
2:ddr3memctrl_inst|Ddr3MemCtrl_pll0:pll0|pll1~PLL_RECONFIG" has 11 connections, but the maximum bus width of port SHIFTEN is 9In the file Ddr3MemCtrl_pll0 there are 11 generic_pll instances and as far as I know the Cyclone Pll has only 9 clock outputs so I assume the error message refers to this and barks about the two additional clock outputs.
In the Megawizard there is no switch to select the number of clock outputs of the hard memory controller.
I tried to synthesise the example created by the Megawizard, but the funny thing is this example is not for the Cyclone V device I specified in Quartus and the fitter ends with an error message too. This time not about the Pll but about some errors with output pins.
So my question is: Has anybody implemented successfully a design with a DDR3 hard memory controller in a Cyclone v device or stumbled on the same error message as above.
Btw. I use Quartus 13.1 according to Altera the latest version but IMHO not the greatest.
Robert