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Cyclone II - PLL differential output

Hi

I have read on this group that it is required 4 pads space from LVDS differential signals to single-ended pin. Is this requirment concern also to PLL_OUTp/n pins?

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PGW
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pgw
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pgw pisze:

Hi,

That's true. If you are not sure just try to fit it. But you can force this if LVDS is next to really slow signals like reset or slow I/O.

Adam

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Górski Adam

I have just do that. This requirment don't concern to PLL_OUT.

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PGW
Reply to
pgw

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