Cyclone 3 on chip termination

Karel,

Cyclone III does not have 3.3v, it only has "3.0 volt IO" -- a new "standard" from Altera! (Stratix III is the same).

Why? Because TSMC does not have a process that has the small fast core transistors, and the larger 3.3v IO transistors.

So, 3.3v is now going the way of 5.0v -- gone. Xilinx still has 3.3v IO at 65nm in Virtex 5, but that is only because we have our own triple oxide process "built to order" by two fabs, UMC and Toshiba.

Good luck!

Austin

Austin,

That is not entirely true. I've used both the Cyclone3 and the Stratix3 with VCCIO at 3.3V. In fact, this is the verbiage used in the S3 spec:

Stratix III devices support a wide range of industry I/O standards. Table 7?1 shows the I/O standards Stratix III devices support as well as the typical applications. Stratix III devices support a VCCIO voltage level of 3.3, 3.0, 2.5, 1.8, 1.5, and 1.2 V.

The issue with the 65nm is that one needs to pay CLOSE attention to over shoot and undershoot voltages. There are three ways to deal with this:

1. Proper termination
2. Clamping diodes
3. Or reduce the VCCIO bank voltage to 3.0V

If you do your job correctly you can run these devices at 3.3V w/o any problems.

Rob

aust> Karel,

You'd better talk to the guys that make the V5 datasheets, because the recommended operating conditions do not leave a lot of room for 3.3V I/ O (3.45V). With both the Cyclone III and Stratix III you are better of at 3.6V recommended maximum input voltage.

With the absolute maximum rating the V5 does a better job. A whole 50 mV more than the Stratix III (4.05V vs 4V). Let's see how Xilinx will do with their Spartan 4 in terms of 3.3V I/O.

Happy reading.

Karl.

To my knowledge the Cyclone III only features the additional I/O features at 3.0V or lower. 3.3V is supported but all clamping, terminating, rail pulling and slew rate compensating has to be done external of the device.

A quick way to check what is and what is not possible is to make a small project within Quartus II with I/O assignments like you want them. Red messages will indicate that the device does not support it...

The 3.3V outputs are limited in drive strength as well.

Karl.

Karl,

Thank you. You broke the code, didn't you?

Remember, Xilinx specifies that at their absolute maximum ratings, the device is still OK, with no reliability issues.

Altera also states that if their parts latch-up (and they do, just search for 'latch up' on their web site), that you, the customer have screwed up, and it is all your fault for "allowing" some overshoot or undershoot....

page 4 (also note how they latch up due to power supply sequencing, etc.)

As a good example of how this lack of margin on IOs and latch up will KILL you: PCI at 3.3V REQUIRES reflective wave switching. That means the inputs have overshoot and undershoot BY DESIGN.

Austin

Careful, this note is quite old (1999). Newer parts do not have power sequencing requirements: read the hot socketing section of any recent Altera chip device handbook.

On the other hand, the 65nm Cyclone-III/Stratix-III 3.3v issue still remains. Basically if you want to use 3.3V PCI on Cyclone-III, use a 3.0V power supply.

Joseph,

Good point (on sequencing).

All I was really trying to point out is that with the shrinking geometries, IO is more often in commonly available foundry processes now using 180nm transistors instead of 250, or 350 nm (.25u or .35u).

And unless the gate thickness is kept as it was in the .35u device, the transistors will just "punch through" (gate rupture, HCI, TDDB, etc.).

Austin

Hi,

Thanks for all this information. I notice that there is some discussion on the possibilities of 3.3V IO with Cyclone 3. What's your experience with 3V3 IO and Cyclone 3, is it just a case of proper termination or are there other problems?

thanks, Karel