Hi all,
Would appreciate a lot if i could get some help on this. Got a couple of questions and have read a lot of those messages on this group on cross clock domain design. Infact I have changed my design to include asynchronous fifo in my design. Now data crossing happens only by the fifo.
But first the clocks. There are three clocks. And the three clocks are getting generated from three DCMs using CLKFX outputs. with the same input clock to three of them
Presently my design works but not always. Sometimes there is the wrong output when i reset the design. i dont think this is the problem of the reset. Also the design is stable at lower frequencies.
The things I have done and experimented are
1.)used LOWSKEWLINES constraint on all the clocks and reset.(my design started working only after this.)oh yeah as well i am using 92% of the slices that is after i included the FIFO. this is ok.2.)have mentioned the period constraint for the input clock to the DCM as well as the PERIOD constraints on the output clocks of the DCM.
3.) included the BRAMS_PORTA constraint for the FIFO. and then associated the clock nets for each of the ports of the FIFO. i think this is how to do it. but in this none of the nets nor instances are included and analyzed. here is the output of the timing analyzerTiming constraint: TS_groupa1 = PERIOD TIMEGRP "clk_fpga" 18.182 nS HIGH 50.000000 % ;
0 items analyzed, 0 timing errors detected.4.) I think the only timing problem affecting my design is the cross clock domain in the FIFO itself. Slack: -11.613ns (requirement - (data path - clock path skew + uncertainty)) Source: receiver/buffercatch/fifo/BU545 (FF) Destination: receiver/buffercatch/fifo/BU216 (FF) Requirement: 0.001ns Data Path Delay: 6.132ns (Levels of Logic = 5) Clock Path Skew: -5.482ns Source Clock: clk_fpga rising at 478487.558ns Destination Clock: clk_datain rising at 478487.559ns Clock Uncertainty: 0.000ns
I am not sure on how to constrain this. The from to constrain and the multicycle constraint will not work with my design because the clocks are not related and there is not a definite time period after which the other clock appears. the clocks are 55,34and 40MHZ.
If anyone feels this problem has been addressed before in a tech document like the xilinx app or anything please let me know the same.
Thank you cheers vasu