Hi
I finally have successfully sythesised my design, unfortunately the critical path seems to be quite long so that i have a low frequency. Can anybody tell me whats the best way to identify the critical path? I used the Xilinx toolsuite, and there is a timing analyser so probably this one is the best bet?
Yes.
Not necessary that the critical path is long a possibility is wrong relative position of clock buffer and clock pin. Timing analyser in ISE is the easiest to use, so you can start with that.
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