Hello,
I am interfacing a XCV1000 to an old MIPS R3000. I am generating a 50 MHz clock using a DLL with an input clock of 25 MHz. The spec for the R3000 requires certain timing for 4 output clocks based on the 50 MHz clock. One clock is the reference 50MHZ clock. Two of the output clocks need to be delayed by 6 ns and the fourth clock by 12 ns. I can use a second DLL to generate 90 and 180 degree phase shifted clocks, but that gives me 5 ns and 10 ns and not 6 ns and 12 ns, respectively. There are some other delayed signals that I need to generate as well. One signal has to lag the 50 MHz clock by 3 ns. Is there a way to easily generate specified signal delays? For registered values, the OFFSET keyword seems to be appropriate, but I am just using output buffers on the clock signals now. This is for a research project using a custom PCB with 4 processor tiles. Each processor tile has 2 XCV1000s, 1 MIPS R3000 and R3010 and SRAMs for the cache. There are also 2 XC2V6000s to control processor communication and a second level of SRAMs. The other approach is inserting buffers and forcing XST to not optimize them away. Are there easier approaches that have worked for others? I am using ISEE 6.3i. I also have access to Modelsim and an oscilloscope.
Thanks for the suggestions, John Davis