Creating Variable Delay for output signals in an XCV1000

Hello,

I am interfacing a XCV1000 to an old MIPS R3000. I am generating a 50 MHz clock using a DLL with an input clock of 25 MHz. The spec for the R3000 requires certain timing for 4 output clocks based on the 50 MHz clock. One clock is the reference 50MHZ clock. Two of the output clocks need to be delayed by 6 ns and the fourth clock by 12 ns. I can use a second DLL to generate 90 and 180 degree phase shifted clocks, but that gives me 5 ns and 10 ns and not 6 ns and 12 ns, respectively. There are some other delayed signals that I need to generate as well. One signal has to lag the 50 MHz clock by 3 ns. Is there a way to easily generate specified signal delays? For registered values, the OFFSET keyword seems to be appropriate, but I am just using output buffers on the clock signals now. This is for a research project using a custom PCB with 4 processor tiles. Each processor tile has 2 XCV1000s, 1 MIPS R3000 and R3010 and SRAMs for the cache. There are also 2 XC2V6000s to control processor communication and a second level of SRAMs. The other approach is inserting buffers and forcing XST to not optimize them away. Are there easier approaches that have worked for others? I am using ISEE 6.3i. I also have access to Modelsim and an oscilloscope.

Thanks for the suggestions, John Davis

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John D. Davis
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Discusses the DCM, and the fixed phase offset feature.

To get 0, 90, 180, 270 use 0 offset.

To get anything else, set the offset to the desired fractional value (8 bits describe the N/256 of a period shift).

For example, 45 degree offset would be 32. 32/256= 1/8 period. 1/8 period = 45/360, or 45 degrees. Then CLK0, CLK2X, CLKDV are all 45 degrees offset, and CLK90 is 135 degrees, CLK180 is 225 degrees, and CLK270 is 315 degrees offset.

You will end up using BUFG's for all clocks to make sure the skew between clocks does not cause you any concerns.

Use two DCMs both driven by the same CLKIN source to get more than 4 separate phases with offsets (drive in parallel).

It is suggested do not place them in tandem, as that increases the jitter. If jitter is not a concern, then use in tandem is OK for the DLL part of the DCM (however do not drive the second DCM input CLKIN from the CLKFX of a first DCM -- that is not guaranteed to work, but CLKIN of the second DCM from CLK0, CLK90, CLK180, CLK270, CLK2X, CLKDV is OK).

Austin

Reply to
austin

Hi Austin,

THanks for the reply. I am using a Virtex I and NOT a Virtex II. I only have DLLs and NOT DCMs so what you have suggested won't work for me.

Do you know of a way to create a arbitrary delay using a combination of DLLs and other delay elements like buffers. My concern is having the backend take out "unnecessary" buffers. I am using app. note 132, which is a very good starting point and implmenents in HW very easily. I need that next step to get the delays specified in the MIPS R3000 timing diagrams.

Thanks, JOhn

John D. Davis PhD Candidate Computer Systems Lab Office # 1.650.723.6891 Stanford University Fax # 1.650.725.6949

Reply to
John D. Davis

John, I would be surprised if the difference between 5 and 6 ns, or between 10 and 12 ns really matters. Do you have a feel for the specification tolerances? Peter Alfke

Reply to
Peter Alfke

Hello,

Because I am working with a prototype system and don't care about temp, voltage and process variation. I am using buffers to insert the delay. I am using the "KEEP" synthesis attribute on the inputs and outputs of the buffers to prevent them from being optimized away. I then use a scope to measure the delay. You can also do post PAR timing simulation, but is not as exact. Finally, I use FPGA Editor to check to see that the singals exist and buffers are mapped to the CLB's.

Cheers, JOhn

John D. Davis PhD Candidate Computer Systems Lab Office # 1.650.723.6891 Stanford University Fax # 1.650.725.6949

Reply to
John D. Davis

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