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Creating own RPMs using Xilinx ISE

Hi,

I am trying to create my own reusable Relationally Placed Macro (RPM) using ISE 6.3.03i without much success. I have followed the procedure defined in the "Creating a reusable RPM core" manual page without much luck.

I am using the "Write RPM to UCF" command in the floorplanner to create the UCF (RLOC'ed) and NGC file. This works fine for a single instantiation connected to the package pins but not for the desired general case of a macro used several times internally to a larger design.

I appear to be getting IIOB & OIOB objects in the NGC netlist for the RPM and cannot get NGDbuild to recognise when it has already used slices in the case where more than one instance is created (suspect not recognising boundary area for RPM?).

If any one has any ideas or a simple example (VHDL preferred)......

Many thanks,

Tim

Reply to
Tim Good
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6.3 has quite a few problems with floorplanning, RPM generation, and multiple RPM instantiation. 7.1 is reported to fix a LOT of these problems, so if you need to use RPMs, I would strongly recommend upgrading to 7.1 at the earliest possible moment.

(the problem you describe below is however NOT a 6.3 bug as far as I can see)

Ah. The RPM is not supposed to contain ANY IOBs. You have to turn OFF IOB instantiation in both the Synthesis and Translate phases (either via command line, or "Properties" for each tool.

You can confirm that IOBs have been successfully disabled in the "map" report file.

Then create the RPM .ngc file as now, and multiple instantiations should work. Connecting up IOBs is best done at the top level.

Even if it is possible to build an RPM with package pins included, and you can live with the restrictions placed on placing the resulting RPMs (they have to be aligned with IOBs!) it is quite likely that tool support for this practice may be buggy.

Here's one - a simple RPM instantiated 8 times in VHDL.

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It illustrates some of the issues which 6.3 had with RPMs, but (if you modify the RPM placements given) shows that it can be done. I look forward to seeing how 7.1 treats this example...

- Brian

Reply to
Brian Drummond

Last I looked, RLOCs and LOCs were incompatible - kind of a problem when your pins are locked down by LOCs :)

Jeremy

Reply to
Jeremy Stringer

We generally avoid doing a true RPM and just use RLOC attributes directly in vhdl. Often if you are doing an RPM you are instantiating primitives anyway so you can easily add the rlocs to the generate loops. The logic still appears as an RPM in floorplanner if you want to place the blocks of rloc'ed logic. Also you can apply LOC attributes to RLOC'ed logic.

This way there are no special steps in the flow. You just pour your vhdl into the synthesis tool like always.

Pete

Reply to
pedro uno

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