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Creating EDIF from VHDL

Hey!

SUpposing im using Xilinx ISE 4.2, how do I go about creating an EDIF file to load into this as thats the only thing I seem to be able to import into the 4.2v

So what do I need to do? somehow find a compiler? or a simulator? will these output and EDIF from my VHDL?

I did a google filetype:edif search to see whether this helps me explain it further to myself, but it seems like a net list or something that you create after placing the cells (or what ever its called) and I havent done that, Ive typed my VHDL and made a UCF file, so what now?

Can anybody give me an overview (ASSII flow chart?? heh) of what I need to do from VHDL to sythesising with ISE 4.2? its the steps in the middle I can't figure out!

sorry everybody!

Sven

Reply to
311f037
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Both Mentor Precision Synthesis and Synplify compile with EDIF as the result.

-a

Reply to
Andy Peters

Sven, approximately the sequence of steps that you go through is this -

You take your VHDL (and constraints file - ucf for a xilinx native flow), and run it through a synthesiser (AFAIK, this is XST for ISE). This gives you a file with a set of primitives relevant to the FPGA you are working with (EDIF for me)).

You then dump it through another couple of tools to get an .ncd, which you run place and route tools on (You may get a few intermediate files - my toolflow differs).

At the other end, you get a .bit, which is the file you load into your FPGA.

Shouldn't the GUI handle this? You probably want to figure out how to get your vhdl files into your project - the ISE toolset should handle the whole process of going from VHDL to bitstream.

The other point is that ISE 4.2 is quite old - you might want to consider getting a more up-to-date set of tools (ex: 7.1 is out at the moment). I know that schematic entry used to be popular - can you confirm that you actually have a synth. tool?

You can download the webpack free from Xilinx, but if you're running foundation, then that has more tools, and you probably want to try getting the setup that you have working first.

Jeremy

Reply to
Jeremy Stringer

Sven's problem is that he is using ISE 4.2, which I am fairly sure did not come with a synthesis tool. I don't really see an easy solution for him. Presumably he is trying to use a very old part, or else I don't understand why he would be using ISE 4.2. A very old part would probably require a very old synthesis tool.

Reply to
Duane Clark

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