creating a seed on a FPGA.

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Hi,

I am aware that the best way to create a seed (for random numbers) is  
external hardware, but does anybody know any cheap-and-easy tricks to  
generate a random-ish number on an FPGA.


Kristoff

Re: creating a seed on a FPGA.
On Thursday, May 4, 2017 at 11:44:54 AM UTC+1, kristoff wrote:
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Read the LSB of the voltage monitoring in xilinx sysmon to get each bit of your number.

Colin

Re: creating a seed on a FPGA.
On Thu, 04 May 2017 07:03:03 -0700, colin wrote:

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Or for sufficiently random request timing, keep a clock running and use  
the clock value for the seed.

Or combine the two.

I seem to remember doing a web search on this a while back -- there are a  
lot of papers, of varying degrees of technical soundness.

--  
www.wescottdesign.com

Re: creating a seed on a FPGA.
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Xilinx has many app notes on this - it's a common requests.
Here's one I've read in the past, but there's others:

http://forums.xilinx.com/xlnx/attachments/xlnx/EDK/27322/1/HighSpeedTrueRandomNumberGeneratorsinXilinxFPGAs.pdf

Regards,

Mark

Re: creating a seed on a FPGA.
On 5/4/2017 11:33 AM, Mark Curry wrote:
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I thought this issue had been solved?

https://xkcd.com/221/

--  

Rick C

Re: creating a seed on a FPGA.

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andomNumberGeneratorsinXilinxFPGAs.pdf
I built a very wide version of this several months ago to do testing in the
 lab but it hasn't been tested yet.  I'll have to report back after my cowo
rkers try it out.  You do have to instantiate LUT primitives to get it to s
ynthesize.  I don't know why the app note didn't address this nor supply an
y example HDL.

Re: creating a seed on a FPGA.
On 05/04/2017 07:03 AM, colin wrote:
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I was going to suggest asynchronous ring oscillator, but yours is  
downright elegant.

--  
Rob Gaddi, Highland Technology -- www.highlandtechnology.com
Email address domain is currently out of order.  See above to fix.

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