Hello fpga-faq,
I want to create a user module that will act as a master on an opb bus. I am using xilinx Platform Studio, version 7.1i. Now before you say it, I have read the
thank you, ~arin
Hello fpga-faq,
I want to create a user module that will act as a master on an opb bus. I am using xilinx Platform Studio, version 7.1i. Now before you say it, I have read the
thank you, ~arin
I have not had much luck with the Xilinx tools for creating peripherals. I would just read
Alan Nishioka
I'm the guy that usually says to use the wizard but its not appropriate for your case. Directly implementing an opb master is quite straightforward--plb is more complicated. The CoreConnect OPB Bus specification will give you all the signals, but OPB has a pretty simple request-grant scheme.
A colleague created a master in HDL to interface with the opb_ddr controller. It was only a couple of lines of code.
Paul
" snipped-for-privacy@hotmail.com" wrote:
Hi , Do u have Xilinx EDK 6.2 tools, in case u have them then , if u go to /hw/XilinxReferenceDesigns/pcores/opb_core_msp0_v1_00_b/ , thats nothing but a OPB Bus Master design with Write capability. The only catch is that it uses a very old version of IPIF. If you are ok with that then you can go ahead and use it. In case u dont have EDK 6.2 , then just send me an e-mail and I can tar the file and send it to you ..
-- Parag Beeraka
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