Active reset is high. In passive state (nRESET) I pull signal to GND with
130k resistor. Pushing a button connects signal to 3.3vcc with 10R in series. Signal is filtered with 0.1uF capasitor. This circuit works well in the absence of CPLD.After plugging power, signal is low (as expected). Pressing the button activates reset. But RESET signal remains ~2.3v after releasing the button. What inside CPLD prevents signal from going down? Seems that 100k-pullup emerges at the input.
CPLD is 9572XL.