I'm trying to produce a square wave clock that is a fifth of the frequency of a faster clock. This means that I must use both the falling edge and rising of the clock. XST complains "Signal cnt cannot be synthesized, bad synchronous description.", I have since learned that I can only have one event per process.
How do I produce a counter that counts on both clock edges?
Regards Andrew
entity div5 is port ( clk : in std_logic; q : out std_logic); end div5;
architecture div5_arch of div5 is signal cnt : std_logic_vector (2 downto 0) := "000";
begin process (clk) begin if(clk'event and clk = '0')then if(cnt = "110") then cnt