Counter ?

Hello, I require a counter which counts up on positive clock; can be reset to zero upon a reset signal; will stop counting when reached max or rollover; will restart counting only after a total reset, which is not the same as the counter reset. (2 resets) Waiting with anticipation. Thanks.

Reply to
<miche>
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Will this do:

formatting link

Cheers, Jon

Reply to
Jon Beniston

Hi Jon, :-) Actually that's quite a useful widget. Ta for the link! Cheers, Syms.

Reply to
Symon

Would you like fries with that also :-)

More seriously, there are a few things you could do to demonstrate that you're not just a lazy person looking for somebody else to do your homework for you:

- Are you using VHDL or Verilog or some schematic-entry tool?

- Have you made any attempt yourself to implement this?

- Can we see your implementation?

- Do you have any simulation stimuli (testbench) to test it?

Reply to
Alan Myler

Yes, verilo

Yes, see my last post 2 day ago.

Yes, see my last post 2 day ago.

Yes, see my last post 2 day ago.

Reply to
<miche>

Miserable gits.

Reply to
<miche>

I wait in anticipation for a link to your previous post 'cos I'm too lazy to search for it.

Reply to
Jon Beniston

repeat(3)

;

Why should anyone *except you* waste time trawling through a NG looking for posts by you, when you can't be bothered to include either a reference or the germane content in your question?

Contrary to what appears to be your opinion, the world does not owe you a living, but only a fair hearing. You'll get that soon enough if you make a fair attempt to be heard.

I could write a solution to your counter problem in considerably less time than it's taken me to write this, but I don't really see the point. Looks like plenty of other people feel pretty much the same way. At least two of the people who replied to this thread have a spectacularly impressive history of pertinent, courteous and expert responses to various questions. The balance of evidence is that it's not *their* fault that you're dissatisfied.

--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
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Reply to
Jonathan Bromley

Jon Beniston ( snipped-for-privacy@beniston.com) wrote: : On 13 Jul, 11:51, wrote: : > Hello, : > I require a counter which counts up on positive clock; : > can be reset to zero upon a reset signal; : > will stop counting when reached max or rollover; : > will restart counting only after a total reset, which is : > not the same as the counter reset. (2 resets) : > Waiting with anticipation. : > Thanks.

: Will this do:

:

formatting link

: Cheers, : Jon

Jon that only has one reset - the OP clearly mentioned that 2 are required...

:)

Cheers, Chris

Reply to
c d saunter

If you were to write the function in C code, what would it look like? I'm hoping you have the software background.

You're working with CPLDs which isn't the typical homework assignment thing. Are you taking your first steps into programmable logic? Are you a hobbyist, electrical engineer, student, or software guy? Knowing this can help us shape our response.

And please start asking questions rather than telling us something and waiting.

- John_H

Reply to
John_H

The question was asked two days ago. I will not repost it. If people can't find it then that's fine.

I need a counter that count up from 0 to 15 When reaching 15 or 0 again - stop Reset1 clears counter to zero Reset2 starts counter Language - verilog

Reply to
<miche>

Hi Miche, A few days ago I posted here a link that explained how to ask technical questions on newsgroups in order to maximise your chance of a useful reply. I will not repost it. If you can't find it then that's fine. HTH, Syms.

Reply to
Symon

Ok, fine ;)

I do that for you according to the following pro forma bill :

- copying example from page 10 of Verilog book.... $10

- adding 5 lines of code $125

- simulation and testing (optional) $50

- shipping and handling (by email) $0.3

- lawyer to sign IP contract & NDA $4000

- writing on a mailing list where at least 300 people can solve your problem in 2 minutes and not getting any answer because you start your message with "I need" and forgot to say "please" ... Priceless !

Reply to
PFC

What are the polarity of the resets?

Does reset1 enable the counter, disable it, or no change?

What are the timing constraints?

How does it reach 0 if counting up?

Are you resets synchronous or asynchronous?

Which clock edge do you wish to count on?

What are the outputs?

Cheers, Jon

Reply to
Jon Beniston

From your earlier response I doubt if this is for real, but I am desperate, so I'll reply

You choose

Reset1 sets the counter to zero, as explained. It does not "enable" it, for this we have reset2

No constraints.

After 15 comes zero

Don't care, whatever is more simple

Don't care

The value of the counter

Reply to
<miche>

How about this?

module counter ( clock, reset1, reset2, counter ); input clock ; input reset1 ; input reset2 ; output [3:0] counter ; wire clock ; wire reset1 ; wire reset2 ; wire [3:0] counter_c; wire GND ; wire enable ; wire VCC ; wire clock_c ; wire reset1_c ; wire reset2_c ; wire un1_counter_1_axbxc0 ; wire un1_counter_1_axbxc1 ; wire un1_counter_1_axbxc2 ; wire N_7_i_i ; wire enablee_0 ; wire G_1_i_a3_0 ; wire G_2_0_o2_0 ; wire GND_Z ; wire VCC_Z ; LUT4_L N_7_i_i_cZ ( .I0(G_2_0_o2_0), .I1(counter_c[0]), .I2(counter_c[1]), .I3(counter_c[3]), .LO(N_7_i_i) ); defparam N_7_i_i_cZ.INIT=16'hBF40; LUT4_L N_6_i ( .I0(G_1_i_a3_0), .I1(counter_c[0]), .I2(counter_c[1]), .I3(enable), .LO(enablee_0) ); defparam N_6_i.INIT=16'h7F00; // @2:10 FDS enable_Z ( .Q(enable), .D(enablee_0), .C(clock_c), .S(reset2_c) ); LUT2_L G_2_0_o2_0_cZ ( .I0(counter_c[2]), .I1(enable), .LO(G_2_0_o2_0) ); defparam G_2_0_o2_0_cZ.INIT=4'h7; LUT2_L G_1_i_a3_0_cZ ( .I0(counter_c[2]), .I1(counter_c[3]), .LO(G_1_i_a3_0) ); defparam G_1_i_a3_0_cZ.INIT=4'h8; // @2:23 LUT2_L un1_counter_1_axbxc0_cZ ( .I0(counter_c[0]), .I1(enable), .LO(un1_counter_1_axbxc0) ); defparam un1_counter_1_axbxc0_cZ.INIT=4'h6; // @2:23 LUT3_L un1_counter_1_axbxc1_cZ ( .I0(counter_c[0]), .I1(counter_c[1]), .I2(enable), .LO(un1_counter_1_axbxc1) ); defparam un1_counter_1_axbxc1_cZ.INIT=8'h6C; // @2:23 LUT4_L un1_counter_1_axbxc2_cZ ( .I0(counter_c[0]), .I1(counter_c[1]), .I2(counter_c[2]), .I3(enable), .LO(un1_counter_1_axbxc2) ); defparam un1_counter_1_axbxc2_cZ.INIT=16'h78F0; // @2:2 BUFGP clock_ibuf ( .I(clock), .O(clock_c) ); // @2:5 OBUF \counter_obuf[3] ( .O(counter[3]), .I(counter_c[3]) ); // @2:5 OBUF \counter_obuf[2] ( .O(counter[2]), .I(counter_c[2]) ); // @2:5 OBUF \counter_obuf[1] ( .O(counter[1]), .I(counter_c[1]) ); // @2:5 OBUF \counter_obuf[0] ( .O(counter[0]), .I(counter_c[0]) ); // @2:4 IBUF reset2_ibuf ( .O(reset2_c), .I(reset2) ); // @2:3 IBUF reset1_ibuf ( .O(reset1_c), .I(reset1) ); // @2:18 FDR \counter_Z[3] ( .Q(counter_c[3]), .D(N_7_i_i), .C(clock_c), .R(reset1_c) ); // @2:18 FDR \counter_Z[2] ( .Q(counter_c[2]), .D(un1_counter_1_axbxc2), .C(clock_c), .R(reset1_c) ); // @2:18 FDR \counter_Z[1] ( .Q(counter_c[1]), .D(un1_counter_1_axbxc1), .C(clock_c), .R(reset1_c) ); // @2:18 FDR \counter_Z[0] ( .Q(counter_c[0]), .D(un1_counter_1_axbxc0), .C(clock_c), .R(reset1_c) ); GND GND_cZ ( .G(GND_Z) ); VCC VCC_cZ ( .P(VCC_Z) ); endmodule /* counter */

Cheers, Jon

Reply to
Jon Beniston

That's very interesting. Is it possible to ask for something which compiles at under 20 lines of code? It's beyond my level of understanding. Thanks.

Reply to
<miche>

I'm SERIOUSLY trying to help here and you completely blew off my other questions in this email AND you have NEVER asked a question that I can recall. A question usually involves a question mark. Are you aware what that is? My apologies if you actually did ask questions in your previous posts, but I recall them all as "This is my situation." "Eagerly anticipating your reply." Please look at my response again from this morning and inform us: from what background do you come and how would you approach this in software (if you know programming languages).

Don't blow off the ones that are trying to help you because others vent their frustration with your inadequate approach to pursuing information from the other posters on this newsgroup.

It's fine if english isn't your first language. It's fine if you're a student. It's fine if you want other people to do your job, just be UP FRONT with this group and we can be a friendly, responsive bunch.

Reply to
John_H

Damn, I was going to suggest this, but it's 26 lines!

module counter ( input wire clock, input wire reset1, input wire reset2, output reg [3:0] counter );

reg enable;

always @(posedge clock) begin if (reset2 == 1'b1) enable

Reply to
Jon Beniston

Hello, I have just tried to compile this, I am receiving 2 warnings

WARNING:ProjectMgmt - "C:/tt/counter/counter.ngr" line 0 duplicate design unit: 'Module|counter' WARNING:ProjectMgmt - "C:/tt/counter/counter.nga" line 0 duplicate design unit: 'Module|counter'

Is this important?

Reply to
<miche>

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