How about this?
module counter ( clock, reset1, reset2, counter ); input clock ; input reset1 ; input reset2 ; output [3:0] counter ; wire clock ; wire reset1 ; wire reset2 ; wire [3:0] counter_c; wire GND ; wire enable ; wire VCC ; wire clock_c ; wire reset1_c ; wire reset2_c ; wire un1_counter_1_axbxc0 ; wire un1_counter_1_axbxc1 ; wire un1_counter_1_axbxc2 ; wire N_7_i_i ; wire enablee_0 ; wire G_1_i_a3_0 ; wire G_2_0_o2_0 ; wire GND_Z ; wire VCC_Z ; LUT4_L N_7_i_i_cZ ( .I0(G_2_0_o2_0), .I1(counter_c[0]), .I2(counter_c[1]), .I3(counter_c[3]), .LO(N_7_i_i) ); defparam N_7_i_i_cZ.INIT=16'hBF40; LUT4_L N_6_i ( .I0(G_1_i_a3_0), .I1(counter_c[0]), .I2(counter_c[1]), .I3(enable), .LO(enablee_0) ); defparam N_6_i.INIT=16'h7F00; // @2:10 FDS enable_Z ( .Q(enable), .D(enablee_0), .C(clock_c), .S(reset2_c) ); LUT2_L G_2_0_o2_0_cZ ( .I0(counter_c[2]), .I1(enable), .LO(G_2_0_o2_0) ); defparam G_2_0_o2_0_cZ.INIT=4'h7; LUT2_L G_1_i_a3_0_cZ ( .I0(counter_c[2]), .I1(counter_c[3]), .LO(G_1_i_a3_0) ); defparam G_1_i_a3_0_cZ.INIT=4'h8; // @2:23 LUT2_L un1_counter_1_axbxc0_cZ ( .I0(counter_c[0]), .I1(enable), .LO(un1_counter_1_axbxc0) ); defparam un1_counter_1_axbxc0_cZ.INIT=4'h6; // @2:23 LUT3_L un1_counter_1_axbxc1_cZ ( .I0(counter_c[0]), .I1(counter_c[1]), .I2(enable), .LO(un1_counter_1_axbxc1) ); defparam un1_counter_1_axbxc1_cZ.INIT=8'h6C; // @2:23 LUT4_L un1_counter_1_axbxc2_cZ ( .I0(counter_c[0]), .I1(counter_c[1]), .I2(counter_c[2]), .I3(enable), .LO(un1_counter_1_axbxc2) ); defparam un1_counter_1_axbxc2_cZ.INIT=16'h78F0; // @2:2 BUFGP clock_ibuf ( .I(clock), .O(clock_c) ); // @2:5 OBUF \counter_obuf[3] ( .O(counter[3]), .I(counter_c[3]) ); // @2:5 OBUF \counter_obuf[2] ( .O(counter[2]), .I(counter_c[2]) ); // @2:5 OBUF \counter_obuf[1] ( .O(counter[1]), .I(counter_c[1]) ); // @2:5 OBUF \counter_obuf[0] ( .O(counter[0]), .I(counter_c[0]) ); // @2:4 IBUF reset2_ibuf ( .O(reset2_c), .I(reset2) ); // @2:3 IBUF reset1_ibuf ( .O(reset1_c), .I(reset1) ); // @2:18 FDR \counter_Z[3] ( .Q(counter_c[3]), .D(N_7_i_i), .C(clock_c), .R(reset1_c) ); // @2:18 FDR \counter_Z[2] ( .Q(counter_c[2]), .D(un1_counter_1_axbxc2), .C(clock_c), .R(reset1_c) ); // @2:18 FDR \counter_Z[1] ( .Q(counter_c[1]), .D(un1_counter_1_axbxc1), .C(clock_c), .R(reset1_c) ); // @2:18 FDR \counter_Z[0] ( .Q(counter_c[0]), .D(un1_counter_1_axbxc0), .C(clock_c), .R(reset1_c) ); GND GND_cZ ( .G(GND_Z) ); VCC VCC_cZ ( .P(VCC_Z) ); endmodule /* counter */
Cheers, Jon