Hi,
I'm trying to implement a second order costas loop for carrier recovery in AM DSB-SC and BPSK. I 've done simulations for AM DSB-SC in MATLAB, but I couldn't implement my design in Xilinx with VHDL. After designing this part for the transmitter, I will design an adaptive equalizer, but I still have serious problems with carrier recovery and have no so much time. I also tried to use System Generator. System Generator has a demo about costas loop, but I couldn't figure it out what kind of logic that it uses. It is a little bit different than typical costas loop model. I would be very greatful if you can share VHDL codes related with carrier recovery or costas loop esp. for AM DSB-SC and BPSK if you have or at least someone please tell me the logic of the costas loop model in system generator demo part. Thanks for your help!
~Emrah