Cost to go from FPGA to ASIC

Both Xilinx and Altera has options to move to ASIC-like implementations from FPGA designs. These chips have a lower unit cost.

Xilinx calls it EasyPath Solution :

. Altera calls it Hardcopy

Very interesting. The Xilinx "EasyPath" seems to be a partialy pre-programmed FPGA. The main (only?) benefit appears to be lower unit cost. There is no power or performance benefit over a standard FPGA.

The Altera "Hardcopy" is closer to a real ASIC, but the up-front costs are also much higher. It will run faster and use less power (~50%) than the same logic in an FPGA.

The up-front cost for "EasyPath" is about $75,000. The up-front cost for "Hardcopy" is about $500,000.

Both of these costs are from Xilinx's website. Altera's site mentions no prices.

Both companies guarantee than if the design works in the FPGA, it will work the same or better in the "ASIC".

Are you sure? I have heard figures of less than half that, but then again my memory is not what it used to be so I could be wrong :-)

Hans.

Depends on the process. For .18, expect to pay $200k.

No. Lots more things can go wrong when making an ASIC.

Depends on the fab. Some will do it, some won't. For those that don't, there are plenty of design services companies that will do it for you.

Depends on your performance requirements.

Fairly easy, but that's because I've always planned ahead, and not used many FPGA specific features. That way, the only things you need to change are memories and I/Os.

Virtex II Pro -7: 150MHz - .13 ASIC - 400 MHz.

Huge amounts. FPGAs suck current like there's no tomorrow.

Cheers, Jon

I am fairly sure about the "EasyPath" cost, since that is from Xilinx's own website.

I am not at all sure about the "Hardcopy" cost, since that is from Xilinx's website too, not Altera's (as I mentioned in my post). Xilinx's cost estimate may put Altera's product in an unfavorable light, but it serves them right. If they want accurate information disseminated, they should provide the information themselves. I could find no price information anywhere on Altera's website.

Anyway, here is my source of information for the cost of both products:

"Kunal" schrieb im Newsbeitrag news: snipped-for-privacy@g49g2000cwa.googlegroups.com...

Xilinx has NO ASIC solutions. The Easypath is an normal FPGA with less testing at the fab. may be atually partially faulty. its only tested to customer bitstream. But the silicon is 1:1 the same as the normal FPGA

antti

There are several smaller companies in the so called conversion business using structured ASICs.

google for 137K hits and more than enough players

AMI, ViaASIC, Flextronic, and also some surprises in the google list like Honeywell and epson I had long forgotten about. The active ones will show up at DAC every year.

For other comments, you could also peek into John Cooleys website, lots of ASIC, EDA vendor feedback there, some very -ve. When you get interested in a particular vendor, research them thouroughly.

Since you mentioned cpu porting, I saw on opencores that the OpenRISC

1200 had been ViaASIC ed so I had a look at that, they reduce it down to a single via mask. They give very little performance info for the conversion though but suggest that most of the expected speed of full std cell is obtained, maybe 20% left behind. This core like most opencores was not planned for FPGA, dates back to the free ASIC IP hubris. A design planned for BlockRam FPGA should port very well to these like minded ASICs if only the mask costs can be lowered.

Their kits are 300-500K $ range for HDL in, GDS out for 1 mask. There have been some poor reviews of this SW, its perhaps still early days.

Not sure how they handle production and quantities, they claim 10x reduction in FPGA costs which shouldn't be too dificult if you have the volume.

One thing that seems obvious is project sharing, if ten projects share

1 mask over a full large die, you could probably get 10-20 designs out of. This is something that maybe the Mosis types should switch too rather than trying to share all masks per group. But if the 10x reduction is spread over 10 projects, back to square one.

What I found interesting was their macro block, something like a 1/4 BlockRam of 128 by 32 DP with around 256 logic cells each includes a FF and handful of gates. I can see right away I would need 2-4 of these for my cpu and that gives me some useful ASIC info to compare against FPGA or other full mask flows, long before I spend any time on ASIC design.

When CA wakes up, somebody from Xilinx will step up to the plate and trash every other vendor.

John

John, CA is waking up, but Xilinx does not intend to "trash every other vendor".

There is room for several approaches, since there are so many variables:

Up-front NRE cost, time-to-market, general risk, acess to the leading-edge technology, and reprogrammability all favor FPGAs, and that's why they are growing faster than the market. Manufacturing cost per chip, speed, and power consumption favor the other approaches.

By aggressively using 90 nm technology, and by incorporating larger functions, our FPGAs have gotten significantly faster and reduced their power consumption and chip area (FIFO controller, PPC, Ethernet controller, multiplier/accumulators, SerDes etc.).

There is room for more than one approach, but the prevailing wind is in favor of the FPGA. Peter Alfke

Antti,

But "partially faulty" yet 99.999% tested (much better than an ASIC is able to be tested) means that any faults which are not being used, don't matter.

Every Altera FPGA sold has a redundant column to replace a faulty one. So, every one they sell could have a fault. But it isn't used. And it does not affect reliability (as shown by their product qual tests).

Easypath has also been fully qualified by the reliability testing that is required of any device.

Aust> "Kunal" schrieb im Newsbeitrag

Jon,

Great post. One comment: the 400 MHz ASIC you propose could also "suck current like there is no tomorrow" if you decide to use all low Vt transistors, and really push the speed (look at any Intel desktop CPU chip). If you just stayed with the 150 MHz number, the current could (should) be quite small, I agree.

Aust>>How much does it cost to produce an ASIC?

I've read criticisms of this "faulty, but tested" thing a number of times in this newsgroup and it surprises me that smart people don't get it.

You provide a final, golden bitstream and Xilinx provide tested, cheaper devices. The parts of the FPGA that are not could be coated in jam for all it matters. The parts that are used are tested.

I'm just a software guy and I get it. How hard can it be?

;-)

Paul,

In all fairness to the people who bring this up (over and over again), is the "fear" that a defect will "develop" or "migrate" or somehow cause a further problem.

That is what process qualification testing is all about. You take the parts that you claim are good for 10, 15, or 20 years, and you test them under commonly accepted conditions to see if you are right.

Every IC manufacturer out there does this.

If we pass XXXX? temp cycles, at YYYY? higher Vcc's, then there are formuals which predict what the worst case failure rate will be. If you have even one failure, the process is reset, corrective actions are made, and you start the test again on the new corrected process parts.

This is not new at all, but something we have all done for years.

Yet, the fear, although irrational (as it applies to every device made in silicon, ever), seems to resonate with people who really don't know "what goes on under the hood."

For some, it is like making sausage, you really don't want to know how it is done.

For others, once you know how it is done, you know the right questions to ask: "Did your EasyPath program go through a standard qual process?"

Answer: "Yes, it did."

Austin

If you can do your own design, it can be a lot cheaper than the figures in some of your replies. We are doing a very tough mixed signal chip with MOSIS, and the base price for the process we are using is about $6000. I'm guessing that you might be able to cram that logic into the minimum chip size (about 16 mm ^2, I think.) Our chip is about 7 x 7 mm, and runs more than the minimum. The tough stuff is the design and mask costs, once they are right, the chips are cheap.

If you roll your own, then success depends on how good and careful you are.

Jon

"Austin Lesea" schrieb im Newsbeitrag news:djqr4n$ snipped-for-privacy@xco-news.xilinx.com...

Hi Austin,

relax -I did not mean to say the easypath are bad or faulty, sure they are fully tested and OK, just they have nothing in common with ASICs.

as of faulty bits - I would welcome if Xilinx would actually sell 'known bad silicon'. That is devices that have either known failures or some % of fails per chip. Such silicon could be sold 'as is'. Saying that this batch has say no more than 3% of LUTS failing, and there are no more than 0.1 interconnect bads... its up to the customer to test the chip and to develop methods how to to use it. I bet Xilinx marketing doesnt like the idea. Idea itself IS GOOD. With proper tools and sw technologies the 'faulty' FPGAs could still be used for many applications.

Antti

Antti,

Selling known bad parts is an interesting concept.

No one has figured out how to do that.

You might talk to Peter about your ideas.

Aust> "Austin Lesea" schrieb im Newsbeitrag

?! - So Xilinx have no errata, on any devices ? Wow ? I'd say pretty much everyone sells bad silicon.

As to selling 'bad by device' [unknown bad parts], that too has been done in Russia.

NAND flash that maps bad sectors in the FAT, is also 'bad by device', so this is not a new, or novel, idea.

The risk to Xilinx is of the parts being relabeled, and sold as genuine, plus all the traffic on how to get these bad xilinx devices to limp along. ie bad for the brand, plus imagine if someone (like Antti) actually got really good at this, and found that a large chunk of sales switched to the low yield El-Cheapo parts - not good for Xilinx's shareholders either....

So I cannot see it happening, but not for technical reasons. Easypath is the closest Xilinx will get.

-jg

Hi Bob,

For Hardcopy, NRE and device price are negotiated on a per-project basis. From my (very limited) experience, $500K for the NRE is grossly exaggerated though.

Best regards,

Ben

Hi Jim

your knowledge still amazes me !

to put thing stright I am not from russia and have nothing todo with them. same for my home country that happened to be occupied by russia for some time. But actually I did enjoy that times as it allowed to travel for virutally free all round the russian territories.

and yes, the russian fabs did sell bad silicon. namly 16kbit, 64kbit and

256kbit DRAMs chips did have special markings indicating if 1) full array is OK 2) lower or upper half is OK 3) single quarter of array is OK

re device re-branding, I guess that is mostly popular in some far east countries that are known to have relabelled intel CPUs at least.

the bad devices idea there are many levels of bad. and different used for bad silicon.

1 like testing of the soldering process. 2 boundary scan test 3 power supply testing

all those can be done with very badly damaged silicon. large altera Stratix devices cost 9,000 USD a piece, I imagine it would be way reasonable to buy bad silicon to pre test a board that is going to be used for a device that cost almost 10K USD a piece.

Antti

PS some posts make me smile, thanks Jim :)

there isnt a smile on face most of the time specially when I am in thinkmode... what is most of the time, and then I look like:

A FPGA which you cant reconfigure ( Not reliably atleast) is "ASIC-like" to me. Anyway i wouldn't to get into a discussion of semantics. I said it would lower unit cost, nothing else. I just showed him the links, he can take it from there.

Kunal