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cosimulation

I am prototyping a IP core which was written in verilog languge in cyclone II FPGA.My application engineer wrote code in C for application level.Can i simulate the both in cadence simulation environment so that i can find the bug in real environment .Can anyone suggest on this.I am in desperate situation.Please help me. Thanking you kumar

Reply to
ram
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I would work on STA and on increasing coverage on my functional fpga and memory testbench. Once that is verified the apps guy can use a software debugger.

-- Mike Treseler

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Mike Treseler

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