Hi,
I wonder why this results in undefined values for some time:
---------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity trigger_level is Port ( clk : in std_logic; prescale : in std_logic; din : in std_logic_vector(7 downto 0); level : in std_logic_vector(7 downto 0); rf : in std_logic; hold : in std_logic; trig : out std_logic); end trigger_level;
architecture Behavioral of trigger_level is type samples_buffer is array(9 downto 0) of std_logic_vector(7 downto 0);
signal samples : samples_buffer; begin
process(clk) begin if rising_edge(clk) and prescale = '1' and hold = '0' then -- no reset circuit (not needed) for reducing the number of slices to 1 instead of 5 for i in 9 downto 1 loop samples(i)