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Coregen Memory Initialization issue

Hi, I am using Coregen (update 3) from within ISE (7.1 update 4). I added a new source from IP, and defined a RAM. This opens the Coregen window, where I can customizet the RAM. I defined the width and depth and added a .coe file for the initial values.

I am sure the format of .coe if perfect, since I can see the coefficients using the button "See coefficients".

However, when I use this RAM in my design (.xco), and try to read the contents, it doesn't seem like they're actually present. At first, I kept reading don't cares and now, somehow, it shows zero initial values.

I use the ISE simulator and I checked the signals down to the memory. Its the memory output which is 0, whereas I was expecting the initial values.

Is the initial value information included only during synthesis or is it used during simulation as well??

Thanks in advance,

Robert.

Reply to
Robert
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Robert,

I have had a similar issue with CoreGen in the past. You can check the

*.edn file to see if it actually initialized. If all of your property INIT strings are zero, it didn't.

The solution for me was to directly edit the *.xco file. CoreGen was setting the load_init_file attribute to false and may have been listing the wrong init file as well. You can directly edit this file and then rerun CoreGen in batch mode.

coregen -b file.xco

Hope this helps, Stephen

Reply to
Stephen Craven

Thanks Stephen.

I checked the .xco file and it looks like the coe file is linked properly.

---------------------.xco file ---------------------- # BEGIN Project Options SET flowvendor = Foundation_iSE SET vhdlsim = True SET verilogsim = True SET workingdirectory = c:\robert_project\other_codes\memory_read_from_ram\tmp SET speedgrade = -4 SET simulationfiles = Behavioral SET asysymbol = True SET addpads = False SET device = xc3s400 SET implementationfiletype = Edif SET busformat = BusFormatAngleBracketNotRipped SET foundationsym = False SET package = pq208 SET createndf = False SET designentry = VHDL SET devicefamily = spartan3 SET formalverification = False SET removerpms = False # END Project Options # BEGIN Select SELECT Single_Port_Block_Memory family Xilinx,_Inc. 6.2 # END Select # BEGIN Parameters CSET handshaking_pins=false CSET init_value=0 CSET coefficient_file=C:\Robert_Project\Other_Codes\memory_read_from_ram\initialize.coe CSET select_primitive=16kx1 CSET initialization_pin_polarity=Active_High CSET global_init_value=0 CSET depth=16 CSET write_enable_polarity=Active_High CSET port_configuration=Read_And_Write CSET enable_pin_polarity=Active_High CSET component_name=my_memory CSET active_clock_edge=Rising_Edge_Triggered CSET disable_warning_messages=true CSET additional_output_pipe_stages=0 CSET limit_data_pitch=18 CSET primitive_selection=Optimize_For_Area CSET enable_pin=true CSET init_pin=false CSET write_mode=Read_After_Write CSET has_limit_data_pitch=false CSET load_init_file=true CSET width=30 CSET register_inputs=false # END Parameters GENERATE

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So I am not sure what's wrong. Is there anything else that need to be checked?

Robert.

Reply to
Robert

I also checked the .edn file and looks like the string is initialized. It does show my initial data in there.

Reply to
Robert

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