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Coregen help

Hi all, I am using the FFT coregen block with pipelined streaming option in my design implementation on a Virtex-4 FPGA. I am having a lot of issues with the implementation and have shortlisted them below:

  1. First of all, the HDL generated file for FFT core 3.2 is not synthesizable. Is there any way to synthesize this block. I am using Xilinx ISE 7.1.4i and latest IP update.
  2. I went back and instantiated the FFT core 3.1 and tried to use that in my design. My PNR report states that the FFT logic is trimmed off. I am not able to understand the problem.
  3. Also, how do I compile the wrapper file?? Please let me know if you have come across this problem. Thanks, Vivek
Reply to
Vivek Menon
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Also the synthesis report shows the following: Reading core . Reading core . Reading core . Reading core . Reading core . Reading core . Reading core . Reading core . Reading core . Reading core . Reading core . Reading core . Reading core . Reading core . Reading core . Reading core . Reading core . Reading module "fifo_memory.ngo" ( "fifo_memory.ngo" unchanged since last run )... Reading core . Loading core for timing and area information for instance . Loading core for timing and area information for instance .

I think this implies that my core is only being read and not loaded. If it's loaded for timing and area information, my core would work.

Thanks > Hi all,

Reply to
Vivek Menon

It's not supposed to be. You need to use the netlist that coregen produces.

/Mikhail

Reply to
MM

Reply to
Vivek Menon

Xilinx protects its IP and will not release synthesizable HDL (or perhaps the source has never been HDL in the first place). Instead you get a netlist file, which you need to add to your project. If you create new source file in ISE with a wizard it's done for you automatically. Otherwise you need to make sure that the macro search path is set properly, so that ISE can find the netlist.

/Mikhail

Reply to
MM

Reply to
Vivek Menon

Usually this means that none of the outputs is used in the design. Could be some mismatch in the component declaration maybe... It's hard to say without seeing the design... Try a minimalist design including the core only and nothing else...

/Mikhail

Reply to
MM

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