Has anyone used the DCT core available in Xilinx ISE 6.1's coregen? I am currently getting the following error message in the translate stage:
ERROR:NgdBuild:604 - logical block 'u2' with type 'DA_2D_DCT' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, or the misspelling of a type name. Symbol 'DA_2D_DCT' is not supported in target 'spartan2'.
I get a similar error message reguardless of the device I select. I instantiate as directed in the .vho file. Does anyone know what I am doing wrong?
Brandon Sterner