Hello,
I'm trying to write a CORDIC macro for a polar transmitter FPGA design. I've used the parallel approach, but when I do a timing estimation the longest delay path is through the CORDIC routine, and limits the maximum clock rate of the whole design to about 40MHz. Other parts of the design on the same board need to run at much faster rate so I'm considering using a bit-serial version.
As I understand it, the bit-parallel implementation has low latency and therefore high throughput, but because of the the word-wide shifts it clocks at a slower rate. Conversely, the bit-serial routine has a high latency and low throughput rate, but allows the board to run at a faster clock rate. Is this right?
My question is:
In the bit-serial implementation, you still need to perform the shift operation on the entire word to select the right bit to send to the bit-serial adder/subtractor, so how does this solve the problem of a slow clock rate due to the shift operation?
Thanks,
Mees