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convert vhdl to edif

hi all,

I am trying to find some means of converting a design described as a vhdl code to edif file. I am using xilinx tool set (from entry to device programming). Are there any other tools that can do the same job.

Thanks! Narayan

Reply to
Narayan
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Synplify will also do it... I don't think that's the answer to your ultimate question though. What are you trying to do?

Jeremy

Reply to
Jeremy Stringer

Narayan,

Let me first ask why?

If you synthesize the design, either ISE or Synplify do generate edif netlist. In ISE, i believe, there is ndg2edif or ngc2edif command or something like this.

Vladislav

Reply to
Vladislav Muravin

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