Conversion of ASIC RTL to FPGA RTL

Hi,

sarath schrieb:

Good ASIC rtl is good FPGA rtl, so you need only a tool allowing you to change the filenames *veg*. In general you need to replace any technologie-dependecies like IO-buffer, PLL, memory,.. to fit your new target technology.

In some cases you might find it necessary to do some greater changes to reach the same performance, but there can be no general advice without knowing exactly all sides of the problem.

bye Thomas

Sarath,

In my humble opinion, a good ASIC RTL design is always going to become a good FPGA RTL design almost at no cost. I mostly did FPGA2ASIC, never done ASIC2FPGA, but I have no doubt about that.

Moving on... You need to think of replacing memories, if they are instantiated as HDL macros, also any PLLs, I/O (if there are any), etc. but the datapath processing should remain the same.

If you can give more details what are you facing, it would be easier to point to the tools, which usually are just a few good engineers.

Vladislav

Hi sarath,

Ususally you don't need a lot of tools to move from ASIC to FPGA.

Most issues arise from design style. The big difference is that ASIC code is usually pretty cost-conscious when it comes to registers (DFFs), while these come for free in an FPGA.Usually, ASIC RTL therefore usually is deeply combinatorial in nature, which can be a performance bottleneck when implemented in an FPGA. FPGA designs tend to be far more pipelined.

Also, 'special' components such as RAM blocks etc will need different names, as well as the fact that you don't need to instantiate your I/O pads. In this case, the tools needed are the data sheets and/or help files from the respective vendors.

Best regards,

Ben

Hi,

Gated-clock conversion to clock-enable structures (most ASIC designs use this especially for low-power). FPGAs do not like gated clocks.

Also, if you have used any standard IP blocks (e.g. Synopsys Designware), that may need to be converted.

--Neeraj