constraints for design-generated clock

Hi,

I am designing a memory controller for a Micron CellularRam and would like to ask what is the best way to generate and what are the optimal buffers, constraints for the clock that needs to be fed to the RAM chip (75 MHz) when operating in synchronous mode and only then. This clock is solely sent to the chip and not used by any other internal logic.

Thanks, Mart

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mludwig
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