hi,
I'm working in VHDL with ISE6.3 and ModelSim5.3. I'm using synchronous and asynchronous reset.
process(clk,ARST) if ARST='1' then
-- elsif rising_edge(clk) then if SRST = '1' then -- else -- end if; end if; end process;
I put constraint on synchronous reset, but I don't know constraints need by an asynchronous reset. When I simulate my design, it's working with the synchronou reset and I have Hold/setup error with asynchronous reset.