hi,
I've have debugging this for the whole afternoonn today, can not get the problem away, becoming crazy.....
I've 1. writen a VHDL-Code for Serial-Parallel-Converter on the Virtex-4 FPGA(Both Pre-SImulation and Post-Simulation pass) 2. downloaded the file to the PROM 3. then feed the CLOCK signal, RESET signal and SERIAL input signal with the Agilent Logic Analyser onto the FPGA 4. and then feed the 16-bits PARALLEL OUTPUT signal and a OUTPUT CLOCK(16 times slowly as input clock) back to the LA.
However, there seems to be something wrong. The output did NOT equal the input.
What the LA send: rst_n clk_sd i_sd
1 0 0 1 1 0 ...