Confused about my behavioral simulation under ISE 9.1

Gang

I created a module, downloaded it to my dev board and ran it. The LED's changed as I expected.

I decided to run a behavioral simulation to prove to myself that signals were changing the way I expected them to.

So I created a verilog test bench. Here is my code.

module tob_tb_v;

// Inputs reg clk; reg rst;

// Outputs wire [7:0] leds;

// Instantiate the Unit Under Test (UUT) Top uut ( .clk(clk), .rst(rst), .leds(leds) );

initial begin // Initialize Inputs

// Wait 100 ns for global reset to finish #100;

$display("At time %t", $time); #10;

$display("At time %t", $time);

// Add stimulus here

end

always @(posedge clk) begin end

endmodule

I am really confused. I have done simulations before on simple modules that didn't have clock inputs. This one as you can see does. When I go to simulation window, I am not seeing a periodic clock signal. Without it, I don't know how to evaluate the state of my other signals.

What am I doing wrong?

Thanks for helping. I am running ISE 9.1 Webpack with SP3, under Windows XP with SP2, 2GB of RAM, 200GB of free disk space.

Bob