Hello everybody,
I am not new to the world of FPGAs but have not found enough literature regarding the SRAMs used for configuration. I need some inputs, help or pointers(papers, articles) from the FPGA community regarding these. There are very few literature relating to this(May be I am not looking in the right places).
- Are these SRAM cells arranged in a big nxn array like normal SRAM memory, or they are in small chunks of memories distributed all over the FPGA layout.
2.Are they physically placed adjacent to their corresponding CLB/Switch boxes.
- As interconnects are fixed after configuration i guess they should always be read only mode, hence should be different from LUTs SRAM cells.
Your inputs will really be helpful to me.
regards
--raj