configuration problem xc2v6000/8000

Hi,

we boot our fpga´s via pci with special boot logic in the pci-spartan. We are using the slave selectmap mode (M[2:0]="110"). Normally the bootprocess and startup works fine - but sometimes there is a mysterious problem:

1.) Done appears and is signalled to the boot device. 2.) FPGA is not working/responding to external requests

This happens 1 of 100 times we boot the fpga, and we have no chance to detect that (without trying some access to the normal IO´s), because we only use the DONE as an indication. The last time this appeared I was clever enough to ask Chipscope to read the status register of all three devices in the additionally available jtag chain. Here are the results (first not working, others do)

COMMAND: show_config_status 0 INFO: Bits [15 ..0]: 0001 1110 1100 1100

Bit 15: 0 RESERVED Bit 14: 0 RESERVED Bit 13: 0 ID_ERROR Bit 12: 1 DONE Bit 11: 1 INIT_B Bit 10: 1 MODE M2 Bit 9: 1 MODE M1 Bit 8: 0 MODE M0 Bit 7: 1 GHIGH_B Bit 6: 1 GWE Bit 5: 0 GTS_CFG Bit 4: 0 IN_ERROR Bit 3: 1 DCI_MATCH Bit 2: 1 DCM_LOCK Bit 1: 0 RESERVED Bit 0: 0 CRC_ERROR COMMAND: show_config_status 1 INFO: Bits [15 ..0]: 0001 1110 1110 1100

Bit 15: 0 RESERVED Bit 14: 0 RESERVED Bit 13: 0 ID_ERROR Bit 12: 1 DONE Bit 11: 1 INIT_B Bit 10: 1 MODE M2 Bit 9: 1 MODE M1 Bit 8: 0 MODE M0 Bit 7: 1 GHIGH_B Bit 6: 1 GWE Bit 5: 1 GTS_CFG Bit 4: 0 IN_ERROR Bit 3: 1 DCI_MATCH Bit 2: 1 DCM_LOCK Bit 1: 0 RESERVED Bit 0: 0 CRC_ERROR COMMAND: show_config_status 2 INFO: Bits [15 ..0]: 0001 1110 1110 1100

Bit 15: 0 RESERVED Bit 14: 0 RESERVED Bit 13: 0 ID_ERROR Bit 12: 1 DONE Bit 11: 1 INIT_B Bit 10: 1 MODE M2 Bit 9: 1 MODE M1 Bit 8: 0 MODE M0 Bit 7: 1 GHIGH_B Bit 6: 1 GWE Bit 5: 1 GTS_CFG Bit 4: 0 IN_ERROR Bit 3: 1 DCI_MATCH Bit 2: 1 DCM_LOCK Bit 1: 0 RESERVED Bit 0: 0 CRC_ERROR

As you can see the GTS_CFG status bit is not set. This means that the IOB´s are not switched into running mode. That makes sense because we see that the IOBs are tristated.On our bitgen option we use the default startup sequence DONE_CYLCLE=4, GTS_CYLCLE=5,GWE_CYCLE=6.

What can cause the fpga not to release the GTS_CFG_B pin? Could it be a timing problem with DONE? Maybe DONE pullup is to weak? We additionally always use DRIVE_DONE, so this should not be the problem.

Any suggestions ?

kind regards, thomas