Configuration of Spartan 3 devices

Hello,

I am considering to use Spartan 3 devices on our new board. Xilinx recommends XCF04S and XCF08P devices for configuration of a Spartan 3

1000. Does anybody know other and cheaper configuration solutions for this FPGA?

thanks and best regards, Dolphin

Reply to
Dolphin
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Dolphin schrieb:

6 (or 8 pin) micro (costs 0.60 USD?) + SPI flash connect SPI DO to DIN, CCLK to SPI CLK, and let the micro to shift in read instruction and release prog_b then, s3 will configure in master serial mode.

antti

Reply to
Antti

or 9536XL CPLD if you need more speed, not much more expensive

Reply to
Mike Harrison

Mike Harrison schrieb:

Or simply use Spartan3E, which can directly interface to cheap SPI Flash?

Regards Falk

Reply to
Falk Brunner

Mike Harrison schrieb:

the speed of the micro is ir-relevant, the FPGA generates the CCLK! thats the beaty, cheapest smallest micro is enough, you only pushin the read command, and let the FPGA todo the rest.

the bitstream can embedded CCLK frequency to swithc to higher configuration clock.

XC9536 are cheap too, but even in smallest package they are rather large compared to tiny micros in QFN 11 or SOT package

Antti

Reply to
Antti

Falk Brunner schrieb:

well the OP wanted S3 so thats not an option,

sure S3E, S3A, V5 all support direct SPI config

Antti

Reply to
Antti

Antti schrieb:

Is it? Says who? I did not hear anything from the OP that prevents the use of a S3E. There are many ways to skin a cat. ;-)

Regardas Falk

Reply to
Falk Brunner

Better make sure the SPI device has a continuous array read command. If you need to read per page, this technique won't work. By the way this sounds like you would need a little bit of extra logic to mux CCLK to the flash? Or were you supposing that the micro would push the command while the CCLK was free-running to the flash? Even at the startup CCLK speed that might require something a little faster than the cheapest smallest micro?

Reply to
Gabor

Falk Brunner schrieb:

OP wanted solution for S3, not for S3e for S3e the SPI flash is obvious, and I bet Xilinx FAE would have suggested it, so I must assume that the S3e wasnt an option and solution was really required for S3

equally well I could say that solution is to use Cyclone or LatticeEC PFGA's as both support SPI loading and are comparable in size to Spartan-3, eg larger than larger device in Spartan3e

Antti

Reply to
Antti

Gabor schrieb:

the micro holds PROG_B active so CCLK is tristated. it takes a few clock cycles of the MCU to shift in the array read and then all it has to be done is to make release the PROG_B the FPGA does the rest at config speed programmed into the BIT file

Antti

Reply to
Antti

Do the S3e parts have the same issue with the overly stiff pullups that the S3 parts have? I'm not sure if they are going to fix that in the S3a parts or not.

Reply to
rickman

Hello,

It is correct that S3E is easier to configure using an SPI flash. Because S3 devices have more IOs than S3E I have to use S3 for this design.

Thanks for the info, Dolphin

Reply to
Dolphin

It was fixed, indeed. The pullups on the S3s were pretty stiff. Things are back toward expectations now with the S3E. I would expect the S3A to follow S3E's lead.

Reply to
John_H

Fixed is a relative term. Worst case for the S3 is 1.4 kohms while the Virtex 4 is 16.5 kohms. The S3E is between at 2.7 kohms, only about 2x the S3 value and under a fifth of the V4 value. I can only assume that there is some issue with the IO design in the Spartan series that makes it hard to get a realisticly useful pullup value around 20 kohms like the V4 and other Xilinx product use. I'm sure we will never know the reason why.

Reply to
rickman

Well, I'm always behind the curve on this stuff, but SST has some VERY cheap flash serial memories. I'm using their 1 Mbit serial flash to config a Spartan 2E chip. I had to make my own device programmer - basically a single CMOS chip used as a level translator and a page of C code to write/read it through a PC parallel port. And, I had to make up a minimal circuit to send a read from address zero command into the chip. That takes two SSOP packages on the board next to the FPGA. These chips can handle up to 25 MHz in their ordinary mode, and up to 32 MHz if you tolerate a one byte delay before output. Nice that Xilinx will waif for a byte of FF before starting to interpret the config bitstream.

I think the 1 MBit chip is about $1.50 in small quantities, I get them from Mouser. They have larger, I don't remember how big they go.

Jon

Reply to
Jon Elson

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