component instantiation ISE7.1

hi, Iam trying to instantiate a component from my user_logic_ip.vhd :

signal h:std_logic_vector(0 to 31); signal k:std_logic_vector(0 to 31); component inv port( x: in std_logic_vector(0 to 31); z: out std_logic_vector(0 to 31)); end component; begin call: inv portmap(h,k); iam giving these h & k values to slv_reg0 & slv_reg1 because i want to give my input from 'C' and see my output on hype terminal. iam using spartan-3 starter kit for download. In ISE Synthesize is going fine but when iam implementing design followin warnings & errors are coming:

NgdBuild:889 - Pad net 'k' is not connected to an external port in this design. A new port 'k' has been added and is connected t this signal. WARNING:NgdBuild:889 - Pad net 'k' is not connected to an external por in this design. A new port 'k' has been added and is connected t this signal. WARNING:NgdBuild:889 - Pad net 'k' is not connected to an external por in this design. A new port 'k' has been added and is connected t this signal.

---------------------all k to k------------------------

ERROR: NgdBuild:809 - output pad net 'k' has an illegal load: pin I2 on block IP2Bus_Data1 with type LUT3 ERROR:NgdBuild:809 - output pad net 'k' has an illegal load: pin I2 on block IP2Bus_Data1 with type LUT3 ERROR:NgdBuild:809 - output pad net 'k' has an illegal load: pin I2 on block IP2Bus_Data1 with type LUT3

--------------------all k to k------------------------

i dont understand what these errors mean...... can anybody help me........... regards gary

Reply to
gary
Loading thread data ...

Could you upload your vhdl file to somewhere?

/Mikhail

Reply to
MM

u want to see the instantiated file it is just a inverter ...

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity inverter is Port ( s : in std_logic_vector(0 to 31); t : out std_logic_vector(0 to 31)); end inverter;

architecture Behavioral of inverter is

begin t

Reply to
gary

No, I wanted to see your userip.vhd, in particular what you are doing with h and k, how they get assigned, etc.

Does the implementation work with the original (wizard generated) userip.vhd?

/Mikhail

Reply to
MM

with h

Iam giving the h,k values to the regesters (slv_reg0,slv_reg1), s that i can throw the input value from the 'C' code to the inverter & se the output of the inverter value on the hyper terminal.

Following is my user_ip.vhd file.. library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all;

library proc_common_v2_00_a; use proc_common_v2_00_a.proc_common_pkg.all;

-- DO NOT EDIT ABOVE THIS LINE --------------------

--USER libraries added here

------------------------------------------------------------------------------

-- Entity section

------------------------------------------------------------------------------

-- Definition of Generics:

-- C_DWIDTH -- User logic data bus width

-- C_NUM_CE -- User logic chip enable bus width

--

-- Definition of Ports:

-- Bus2IP_Clk -- Bus to IP clock

-- Bus2IP_Reset -- Bus to IP reset

-- Bus2IP_Data -- Bus to IP data bus for user logic

-- Bus2IP_BE -- Bus to IP byte enables for use logic

-- Bus2IP_RdCE -- Bus to IP read chip enable for use logic

-- Bus2IP_WrCE -- Bus to IP write chip enable for use logic

-- IP2Bus_Data -- IP to Bus data bus for user logic

-- IP2Bus_Ack -- IP to Bus acknowledgement

-- IP2Bus_Retry -- IP to Bus retry response

-- IP2Bus_Error -- IP to Bus error response

-- IP2Bus_ToutSup -- IP to Bus timeout suppress

------------------------------------------------------------------------------

entity user_logic is generic ( -- ADD USER GENERICS BELOW THIS LINE --------------- --USER generics added here -- ADD USER GENERICS ABOVE THIS LINE ---------------

-- DO NOT EDIT BELOW THIS LINE --------------------- -- Bus protocol parameters, do not add to or delete C_DWIDTH : integer := 32; C_NUM_CE : integer := 3 -- DO NOT EDIT ABOVE THIS LINE --------------------- ); port ( -- ADD USER PORTS BELOW THIS LINE ------------------ --USER ports added here -- ADD USER PORTS ABOVE THIS LINE ------------------

-- DO NOT EDIT BELOW THIS LINE --------------------- -- Bus protocol ports, do not add to or delete Bus2IP_Clk : in std_logic; Bus2IP_Reset : in std_logic; Bus2IP_Data : in std_logic_vector(0 t C_DWIDTH-1); Bus2IP_BE : in std_logic_vector(0 t C_DWIDTH/8-1); Bus2IP_RdCE : in std_logic_vector(0 t C_NUM_CE-1); Bus2IP_WrCE : in std_logic_vector(0 t C_NUM_CE-1); IP2Bus_Data : out std_logic_vector(0 t C_DWIDTH-1); IP2Bus_Ack : out std_logic; IP2Bus_Retry : out std_logic; IP2Bus_Error : out std_logic; IP2Bus_ToutSup : out std_logic -- DO NOT EDIT ABOVE THIS LINE --------------------- ); end entity user_logic;

------------------------------------------------------------------------------

-- Architecture section

------------------------------------------------------------------------------

architecture IMP of user_logic is

--USER signal declarations added here, as needed for user logic

------------------------------------------ -- Signals for user logic slave model s/w accessible register example ------------------------------------------ signal slv_reg0 : std_logic_vector(0 to C_DWIDTH-1);

signal slv_reg1 : std_logic_vector(0 to C_DWIDTH-1);

signal slv_reg2 : std_logic_vector(0 to C_DWIDTH-1);

signal slv_reg_write_select : std_logic_vector(0 to 2); signal slv_reg_read_select : std_logic_vector(0 to 2); signal slv_ip2bus_data : std_logic_vector(0 to C_DWIDTH-1);

signal slv_read_ack : std_logic; signal slv_write_ack : std_logic; signal h : std_logic_vector(0 to 31); signal k : std_logic_vector(0 to 31); component inverter port( s : in std_logic_vector(0 to 31); t : out std_logic_vector(0 to 31)); end component;

begin

we: inverter port map(h,k);

--USER logic implementation added here

------------------------------------------ -- Example code to read/write user logic slave model s/w accessible registers

-- -- Note: -- The example code presented here is to show you one way of reading/writing

-- software accessible registers implemented in the user logic slave model.

-- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond

-- to one software accessible register by the top level template. For example,

-- if you have four 32 bit software accessible registers in the user logic, you

-- are basically operating on the following memory mapped registers: -- -- Bus2IP_WrCE or Memory Mapped -- Bus2IP_RdCE Register -- "1000" C_BASEADDR + 0x0 -- "0100" C_BASEADDR + 0x4 -- "0010" C_BASEADDR + 0x8 -- "0001" C_BASEADDR + 0xC -- ------------------------------------------ slv_reg_write_select

Reply to
gary

Gary,

h doesn't have a source in your code. You need to add something like this: h

Reply to
MM

this:

read

In user_ip.vhd file i used the following instantation in user logi implementation h

Reply to
gary

Gary,

It seems you are thinking as if you were writing software. VHDL is a hardware description language. You need to understand what hardware you are trying to create. You have a separate write and read processes, which essentially describe behaviour of a bunch (because you have more than a single bit) of D flip-flops. The write process describes what is applied to the D input and the read process what happens to the Q output. Thus, when you see slv_reg in the write process on the left side of the assignment it represents the D-input of the flip-flop, while when you see it on the right side in the read process it represents the Q output of the same flip-flop, i.e. stored content of the register.

/Mikhail

Reply to
MM

are

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flip-flop,

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my

sorry iam a beginner, thanks for ur information.In m user_ip.vhd there are 2 process one for read & another for write, now want to access my inverter i.e one i/p & one o/p. so i have to write lik this (h

Reply to
gary

No, it's not. See below corrected write and read processes and assignement for h.

====================================================== -- implement slave model register(s) SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is begin

if Bus2IP_Clk'event and Bus2IP_Clk = '1' then if Bus2IP_Reset = '1' then slv_reg0 '0'); else case slv_reg_write_select is when "100" =>

for byte_index in 0 to (C_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg0(byte_index*8 to byte_index*8+7) null; end case; end if; end if;

end process SLAVE_REG_WRITE_PROC;

h slv_ip2bus_data slv_ip2bus_data slv_ip2bus_data '0'); end case;

end process SLAVE_REG_READ_PROC;

======================================================

/Mikhail

Reply to
MM

hi, I did it in the same way what you have told, synthesis is going wel but while implementing design i stucked up at following errors:

ERROR:NgdBuild:809 - output pad net 'k' has an illegal load: ERROR:NgdBuild:809 - output pad net 'k' has an illegal load: ERROR:NgdBuild:455 - logical net 'slv_reg0' has multiple driver(s): ERROR:NgdBuild:924 - input pad net 'slv_reg0' is driving non-buffer ERROR:NgdBuild:809 - output pad net 'k' has an illegal load: ERROR:NgdBuild:809 - output pad net 'k' has an illegal load: ERROR:NgdBuild:809 - output pad net 'k' has an illegal load: ERROR:NgdBuild:809 - output pad net 'k' has an illegal load: ERROR:NgdBuild:455 - logical net 'slv_reg0' has multiple driver(s): ERROR:NgdBuild:924 - input pad net 'slv_reg0' is driving non-buffer ERROR:NgdBuild:455 - logical net 'slv_reg0' has multiple driver(s): ERROR:NgdBuild:924 - input pad net 'slv_reg0' is driving non-buffer ERROR:NgdBuild:455 - logical net 'slv_reg0' has multiple driver(s): ERROR:NgdBuild:924 - input pad net 'slv_reg0' is driving non-buffer ERROR:NgdBuild:455 - logical net 'slv_reg0' has multiple driver(s): ERROR:NgdBuild:924 - input pad net 'slv_reg0' is driving non-buffer ERROR:NgdBuild:809 - output pad net 'k' has an illegal load: ERROR:NgdBuild:455 - logical net 'slv_reg0' has multiple driver(s): ERROR:NgdBuild:924 - input pad net 'slv_reg0' is driving non-buffer ERROR:NgdBuild:809 - output pad net 'k' has an illegal load: ERROR:NgdBuild:455 - logical net 'slv_reg0' has multiple driver(s): ERROR:NgdBuild:924 - input pad net 'slv_reg0' is driving non-buffer ERROR:NgdBuild:809 - output pad net 'k' has an illegal load: ERROR:NgdBuild:455 - logical net 'slv_reg0' has multiple driver(s): ERROR:NgdBuild:924 - input pad net 'slv_reg0' is driving non-buffer ERROR:NgdBuild:809 - output pad net 'k' has an illegal load: ERROR:NgdBuild:455 - logical net 'slv_reg0' has multiple driver(s): ERROR:NgdBuild:924 - input pad net 'slv_reg0' is driving non-buffer ERROR:NgdBuild:455 - logical net 'slv_reg0' has multiple driver(s): ERROR:NgdBuild:924 - input pad net 'slv_reg0' is driving non-buffer ERROR:NgdBuild:455 - logical net 'slv_reg0' has multiple driver(s): ERROR:NgdBuild:924 - input pad net 'slv_reg0' is driving non-buffer ERROR:NgdBuild:455 - logical net 'slv_reg0' has multiple driver(s): ERROR:NgdBuild:924 - input pad net 'slv_reg0' is driving non-buffer ERROR:NgdBuild:809 - output pad net 'k' has an illegal load: ERROR:NgdBuild:455 - logical net 'slv_reg0' has multiple driver(s): ERROR:NgdBuild:924 - input pad net 'slv_reg0' is driving non-buffer ERROR:NgdBuild:455 - logical net 'slv_reg0' has multiple driver(s): ERROR:NgdBuild:924 - input pad net 'slv_reg0' is driving non-buffer ERROR:NgdBuild:455 - logical net 'slv_reg0' has multiple driver(s): ERROR:NgdBuild:924 - input pad net 'slv_reg0' is driving non-buffer ERROR:NgdBuild:455 - logical net 'slv_reg0' has multiple driver(s): ERROR:NgdBuild:924 - input pad net 'slv_reg0' is driving non-buffer ERROR:NgdBuild:455 - logical net 'slv_reg0' has multiple driver(s): ERROR:NgdBuild:924 - input pad net 'slv_reg0' is driving non-buffer ERROR:NgdBuild:455 - logical net 'slv_reg0' has multiple driver(s): ERROR:NgdBuild:924 - input pad net 'slv_reg0' is driving non-buffer ERROR:NgdBuild:455 - logical net 'slv_reg0' has multiple driver(s): ERROR:NgdBuild:924 - input pad net 'slv_reg0' is driving non-buffer ERROR:NgdBuild:809 - output pad net 'k' has an illegal load: ERROR:NgdBuild:809 - output pad net 'k' has an illegal load: ERROR:NgdBuild:455 - logical net 'slv_reg0' has multiple driver(s): ERROR:NgdBuild:924 - input pad net 'slv_reg0' is driving non-buffer ERROR:NgdBuild:455 - logical net 'slv_reg0' has multiple driver(s): ERROR:NgdBuild:924 - input pad net 'slv_reg0' is driving non-buffer ERROR:NgdBuild:809 - output pad net 'k' has an illegal load: ERROR:NgdBuild:809 - output pad net 'k' has an illegal load: ERROR:NgdBuild:455 - logical net 'slv_reg0' has multiple driver(s): ERROR:NgdBuild:924 - input pad net 'slv_reg0' is driving non-buffer ERROR:NgdBuild:809 - output pad net 'k' has an illegal load: ERROR:NgdBuild:809 - output pad net 'k' has an illegal load: ERROR:NgdBuild:809 - output pad net 'k' has an illegal load: ERROR:NgdBuild:809 - output pad net 'k' has an illegal load: ERROR:NgdBuild:809 - output pad net 'k' has an illegal load: ERROR:NgdBuild:809 - output pad net 'k' has an illegal load: ERROR:NgdBuild:809 - output pad net 'k' has an illegal load: ERROR:NgdBuild:455 - logical net 'slv_reg0' has multiple driver(s): ERROR:NgdBuild:924 - input pad net 'slv_reg0' is driving non-buffer ERROR:NgdBuild:809 - output pad net 'k' has an illegal load: ERROR:NgdBuild:455 - logical net 'slv_reg0' has multiple driver(s): ERROR:NgdBuild:924 - input pad net 'slv_reg0' is driving non-buffer ERROR:NgdBuild:809 - output pad net 'k' has an illegal load: ERROR:NgdBuild:809 - output pad net 'k' has an illegal load: ERROR:NgdBuild:455 - logical net 'slv_reg0' has multiple driver(s): ERROR:NgdBuild:924 - input pad net 'slv_reg0' is driving non-buffer ERROR:NgdBuild:809 - output pad net 'k' has an illegal load: ERROR:NgdBuild:809 - output pad net 'k' has an illegal load: ERROR:NgdBuild:455 - logical net 'slv_reg0' has multiple driver(s): ERROR:NgdBuild:924 - input pad net 'slv_reg0' is driving non-buffer ERROR:NgdBuild:809 - output pad net 'k' has an illegal load: ERROR:NgdBuild:809 - output pad net 'k' has an illegal load: ERROR:NgdBuild:455 - logical net 'slv_reg0' has multiple driver(s): ERROR:NgdBuild:924 - input pad net 'slv_reg0' is driving non-buffer ERROR:NgdBuild:809 - output pad net 'k' has an illegal load: ERROR:NgdBuild:455 - logical net 'slv_reg0' has multiple driver(s): ERROR:NgdBuild:924 - input pad net 'slv_reg0' is driving non-buffer ERROR:NgdBuild:455 - logical net 'slv_reg0' has multiple driver(s): ERROR:NgdBuild:924 - input pad net 'slv_reg0' is driving non-buffer ERROR:NgdBuild:809 - output pad net 'k' has an illegal load: ERROR:NgdBuild:455 - logical net 'slv_reg0' has multiple driver(s): ERROR:NgdBuild:924 - input pad net 'slv_reg0' is driving non-buffer ERROR:NgdBuild:809 - output pad net 'k' has an illegal load: ERROR:NgdBuild:455 - logical net 'slv_reg0' has multiple driver(s): ERROR:NgdBuild:924 - input pad net 'slv_reg0' is driving non-buffer ERROR:NgdBuild:455 - logical net 'slv_reg0' has multiple driver(s): ERROR:NgdBuild:924 - input pad net 'slv_reg0' is driving non-buffer ERROR: NGDBUILD failed

shall i add any user ports in my design? as of i know user ports are necessary when iam accessing any ports outside the FPGA.

But iam just instantiating the component in my ip, so its a internal logic.

can you suggest me? /gary

Reply to
gary

The multiple driver errors seem to say that you still have wrong assignments in your code, i.e. you have slv_reg0 on the left side of the equation in more than one place...

I am not sure about other errors... Try to clean this one first...

/Mikhail

Reply to
MM

my problem is solved, itz not the problem with my code. Th componet which iam adding (i.e inverter.vhd) synthesize this file befor adding to user_logic.vhd file,so that it will generate edif or ngc file known as netlist files,that can be used in synthesis. After doing thi right click on the inverter.vhd file and click the option 'move to surce add it to ur core. Then it works fine!

regards gary

Reply to
gary

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