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Completed my first Virtex4 design

Well, Xilinx shipped me my Foundation 6.3i software update, and since it has the initial support for Virtex 4, I installed it and did a design.

Here it is:

====

module top(in_bus,out_bus); input [15:0] in_bus; output [15:0] out_bus;

assign out_bus = {in_bus[14:0],in_bus[15]};

endmodule

====

Par Report (trimmed):

Release 6.3i Par G.35 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Thu Sep 02 19:16:08 2004 Loading device database for application Par from file "top_map.ncd". "top" is an NCD, version 2.38, device xc4vfx12, package sf363, speed -11 Loading device for application Par from file '4vfx12.nph' in environment Device speed data version: PREVIEW 1.46 2004-07-09. Device utilization summary: Number of External IOBs 32 out of 240 13% Number of LOCed External IOBs 0 out of 32 0%

Total REAL time to PAR completion: 19 secs Total CPU time to PAR completion: 18 secs

Peak Memory Usage: 105 MB

Placement: Completed - No errors found. Routing: Completed - No errors found.

====

Some of the manuals are single page PDFs, that point you to the web site to get the real thing.

Although you all do HDL designs only, you might want to get the Schematic Designers library guide as well as the HDL guide, as the HDL one is 290 pages, and the schematic one is 700 pages. Most of the extra stuff is stuff you don't need, such as 4 bit counter macros, but there are also some things that are pretty interesting that seem to have been left out of the HDL version. Probably fixed in the next version.

FPGA editor shows lots of interesting new stuff. Still waiting for a data sheet, as the FPGA editor shows you details of the forest from the perspective of having your nose pressed against a huge tree :-) and the library guides is mostly very detailed for simple stuff like logic and FF primitives, and not nearly as much info as you might want for the complex stuff.

If this is the sort of thing you like, then you will probably like this sort of thing.

Philip

Philip Freidin Fliptronics

Reply to
Philip Freidin
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Wot, No Speed reports ? You should try a 32 bit ctr, and see what it reports :)

-jg

Reply to
Jim Granville

Ugh! I always hate that sort of thing. CDs are cheap, they should include the real docs. (It's all well and good to suggest looking at the web site for updates.)

What happens in five years when a customer needs you to revise an old design? You discover that Foundation ISE 11.2 doesn't support the old parts, or that for some reason the old design doesn't build right with it, so you get out your old CD of ISE 6.3. And then discover that you don't have the actual documentation.

Years ago people told me that as more and more information became available digitally, particular works would be available on a permanent basis, because storage capacity and bandwidth keep increasing, and there's no longer an reason why things should go out of print. The publisher doesn't have to keep a warehouse of books that only sell a copy occasionally; instead it is just bits on a hard drive.

While there may be some small amount of truth to that, the reality is that most digital works are even more ephemeral than the paper they are replacing.

Sigh.

Reply to
Eric Smith

Sure, with an input register and output register to isolate the counter performance from the I/O performance.

Set clock period goal to 250 MHz.

==== module top(in_bus,out_bus,clock);

input [31:0] in_bus; output [31:0] out_bus; input clock;

reg [31:0] counter; reg [31:0] in_bus_reg; reg [31:0] out_bus_reg;

always @(posedge clock) begin counter Some of the manuals are single page PDFs, that point you to

This is clearly not a CD issue. Most of the manuals are included. The ones that were stubbed, are the ones that were obviously not ready at the time they had everything else ready to commit to CD.

These are basically the Virtex-4 library guides.

You can get them here:

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Well, I'm sure they will be in the 6.3.n sub release, and for older versions of the software, you can go here:

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or

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for even older stuff.

Philip

Philip Freidin Fliptronics

Reply to
Philip Freidin

Philip,

If you get a chance, play with the DSP blocks. The speeds > Well,

--

--Ray Andraka, P.E. President, the Andraka Consulting Group, Inc.

401/884-7930 Fax 401/884-7950 email snipped-for-privacy@andraka.com
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Ray Andraka

Reply to
Symon

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