Compiling Altera LPM FIFO into Modelsim Error

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To all,

  I have been attempting to load a lpm component into a Modelsim
project and when I get my test bench compiled and I try to simulate, I
get the following error.  Note that vosq0_prestore_fifo (my own name)
is an instantiated VHDL LPM component from Altera Quartus software
using their scfifo function.  Below shows the log window.  The fatal
error is shown below and is detailed because for some reaoson I don't
know where to declare a value for the LPM_WIDTHU variable?  I had
thought that this was already defined?  Your help would be appreciated.

Cheers
Pino

# Loading work.vosq0_prestore_fifo(rtl)
# Refreshing
C:/altera/modeltech_ae/altera/vhdl/altera_mf.altera_mf_components
# Loading
C:/altera/modeltech_ae/altera/vhdl/altera_mf.altera_mf_components
# Loading work.vosq0_prestore_fifo_dcfifo_dsu(rtl)
# Loading work.vosq0_prestore_fifo_a_gray2bin_fl6(rtl)
# Refreshing
C:/altera/modeltech_ae/altera/vhdl/altera_mf.a_graycounter(behavior)
# Loading
C:/altera/modeltech_ae/altera/vhdl/altera_mf.a_graycounter(behavior)
# Refreshing
C:/altera/modeltech_ae/altera/vhdl/altera_mf.altera_common_conversion(body)
# Loading
C:/altera/modeltech_ae/altera/vhdl/altera_mf.altera_common_conversion(body)
# Refreshing
C:/altera/modeltech_ae/altera/vhdl/altera_mf.altera_device_families(body)
# Loading
C:/altera/modeltech_ae/altera/vhdl/altera_mf.altera_device_families(body)
# Refreshing
C:/altera/modeltech_ae/altera/vhdl/altera_mf.altsyncram(translated)
# Loading
C:/altera/modeltech_ae/altera/vhdl/altera_mf.altsyncram(translated)
# Loading work.vosq0_prestore_fifo_alt_synch_pipe_lb5(rtl)
# Loading work.vosq0_prestore_fifo_dffpipe_lb5(rtl)
# Loading
C:/altera/modeltech_ae/altera/vhdl/220model.lpm_common_conversion(body)
# Loading
C:/altera/modeltech_ae/altera/vhdl/220model.lpm_counter(lpm_syn)
# Refreshing
C:/altera/modeltech_ae/altera/vhdl/altera_mf.scfifo(behavior)
# Loading C:/altera/modeltech_ae/altera/vhdl/altera_mf.scfifo(behavior)
# ** Fatal: (vsim-3350) Generic 'lpm_widthu' has not been given a
value.
#    Time: 0 ns  Iteration: 0  Instance:
/tb_sopc_memory_rw_vhdl/write_fifo_vosq0/vosq0_prestore_fifo_dcfifo_dsu_component/scfifo14
File:
QuartusIIVersion4.0(C:/Modeltech_6.0/win32/../altera/Vhdl/src/altera_mf/altera_mf.vhd)
# FATAL ERROR while loading design


Re: Compiling Altera LPM FIFO into Modelsim Error
lpm_widthu will be a generic in the scfifo .. if you look at the entity for
the scfifo it should show the available generics.

Quoted text here. Click to load it
C:/altera/modeltech_ae/altera/vhdl/altera_mf.altera_common_conversion(body)
Quoted text here. Click to load it
C:/altera/modeltech_ae/altera/vhdl/altera_mf.altera_common_conversion(body)
Quoted text here. Click to load it
/tb_sopc_memory_rw_vhdl/write_fifo_vosq0/vosq0_prestore_fifo_dcfifo_dsu_comp
onent/scfifo14
Quoted text here. Click to load it
QuartusIIVersion4.0(C:/Modeltech_6.0/win32/../altera/Vhdl/src/altera_mf/alte
ra_mf.vhd)
Quoted text here. Click to load it



Re: Compiling Altera LPM FIFO into Modelsim Error
The lpm_widthu parameter need sto be calculated & set by MegaWizard based on
the size
of FIFO chosen by the user.

Quoted text here. Click to load it

The design should be modified through the scfifo MegaWizard and should not
changed manually.

Hope this helps,
Subroto Datta
Altera Corp.

Quoted text here. Click to load it
/tb_sopc_memory_rw_vhdl/write_fifo_vosq0/vosq0_prestore_fifo_dcfifo_dsu_component/scfifo14
Quoted text here. Click to load it
QuartusIIVersion4.0(C:/Modeltech_6.0/win32/../altera/Vhdl/src/altera_mf/altera_mf.vhd)
Quoted text here. Click to load it



Re: Compiling Altera LPM FIFO into Modelsim Error
Hi All,

    The specific error here was resolved by including the altera_mf
library into my test bench VHDL code.  I also needed to include the USE
altara_mf.altera_mf_components.all into the VHDL code.

    Unfortunately when it does compile, there is another error that
appears which is bizarre.  The Modelsim error is 3473 as follows:

# ** Warning: (vsim-3473) Component 'a_graycounter2' is not bound.
#    Time: 0 ns  Iteration: 0  Region:
/tb_sopc_memory_rw_vhdl/write_fifo_vosq0/vosq0_prestore_fifo_dcfifo_dsu_component
 File: D:/My
Documents/University/Masters_Project/VHDL_Coding/Prestore_FIFO/vosq0_prestore_fifo.vhd

   The error by Modelsim is described as follows:
# The specified component has not been explicitly bound and no default
# binding has been found for it. This means that your VHDL design does
# not include a component configuration for the specified component
that
# indicates which entity/architecture to use for that component. It
also
# means that no entity of the specified name containing ports and
generics
# matching those in the component declaration was found when searching
all
# visible libraries for a default binding. Simulation will continue,
but
# no VHDL code will be executed for the unbound component.
#
# To fix this problem, either put a component configuration in your
VHDL
# design that specifies which entity/architecture to use for this
component
# or compile an entity of the same name as the component and containing
# ports and generics matching those in the component declaration along
# with at least one architecture for the entity into a library that is
# visible at the time the component is being elaborated. You may need
# to add a library use clause before the entity containing the unbound
# component in order to make the library and component visible.


   When I go and view the VHDL code that was generated by the Quartus
megawizard for the FIFO, it seems that the VHDL code for my FIFO
appears to have the instantiation of all the libraries including the
one that I described above, which dictates that the entity/architecture
code should be detectable by Modelsim during the compile process.  I'm
confused to why this is not happening?   Is there another library that
I missed?

Just so it's clear my VHDL testbench also includes the following:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE std.textio.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_arith.ALL;

LIBRARY lpm;
USE lpm.lpm_components.all;

LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;


Regards
Pino



Subroto Datta wrote:
Quoted text here. Click to load it
/tb_sopc_memory_rw_vhdl/write_fifo_vosq0/vosq0_prestore_fifo_dcfifo_dsu_component/scfifo14
Quoted text here. Click to load it
QuartusIIVersion4.0(C:/Modeltech_6.0/win32/../altera/Vhdl/src/altera_mf/altera_mf.vhd)
Quoted text here. Click to load it


Re: Compiling Altera LPM FIFO into Modelsim Error
When there is a binding error..  this usually points to a connection
problem.  Typical things to look for are std_logic vrs std_ulogic ints
unsigned vrs signed.  This part is very much like OOP where the compiler is
looking for a component with the exact same connections.  The ieee sometimes
does the conversion for you so it can be hidden sometimes.
(if you use std_logic_unsigned you will find you can add an integer to a
std_logic_vector for example)


Simon


Quoted text here. Click to load it
/tb_sopc_memory_rw_vhdl/write_fifo_vosq0/vosq0_prestore_fifo_dcfifo_dsu_comp
onent
Quoted text here. Click to load it
Documents/University/Masters_Project/VHDL_Coding/Prestore_FIFO/vosq0_prestor
e_fifo.vhd
Quoted text here. Click to load it
based on
not
appreciated.
C:/altera/modeltech_ae/altera/vhdl/altera_mf.altera_common_conversion(body)
Quoted text here. Click to load it
C:/altera/modeltech_ae/altera/vhdl/altera_mf.altera_common_conversion(body)
Quoted text here. Click to load it
C:/altera/modeltech_ae/altera/vhdl/altera_mf.altera_device_families(body)
Quoted text here. Click to load it
C:/altera/modeltech_ae/altera/vhdl/altera_mf.altera_device_families(body)
Quoted text here. Click to load it
C:/altera/modeltech_ae/altera/vhdl/220model.lpm_common_conversion(body)
Quoted text here. Click to load it
C:/altera/modeltech_ae/altera/vhdl/altera_mf.scfifo(behavior)
Quoted text here. Click to load it
/tb_sopc_memory_rw_vhdl/write_fifo_vosq0/vosq0_prestore_fifo_dcfifo_dsu_comp
onent/scfifo14
Quoted text here. Click to load it
QuartusIIVersion4.0(C:/Modeltech_6.0/win32/../altera/Vhdl/src/altera_mf/alte
ra_mf.vhd)
Quoted text here. Click to load it



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