Compile error by Cadence NC-Sim

hi, everyone,

I want to compile two VHDL-Code, and the Xilinx simprim library into my design.

  1. hdl.var: DEFINE WORK worklib DEFINE LIB_MAP($LIB_MAP, \ $XILINX/verilog/src/simprims => SIMPRIM_VER, \

src/fprint.vhd => FPRINT, \ src/fprint_body.vhd => FPRINT)

  1. cds.lib SOFTINCLUDE .../cds.lib DEFINE std ... ... DEFINE worklib /.../publib/worklib DEFINE SIMPRIM_VER /.../publib/simprim_ver DEFINE FPRINT /.../publib/fprint

  1. ncvlog.options

-messages

-status

-sv31a

-linedebug

-cdslib cds.lib // Use the specified cds.lib file

-hdlvar hdl.var // Use the specified hdl.var file

-logfile ncvlog.log // Files to be compiled: $XILINX/verilog/src/simprims/*.v

  1. ncvhdl.options

-messages

-status

-v93

-linedebug

-assert

-cdslib cds.lib

-hdlvar hdl.var

-logfile ncvhdl.log

// Files to be compiled: src/fprint.vhd src/fprint_body.vhd

  1. c-shell script under unix #!/bin/csh -f clear ncvlog -f ncvlog.options # Compile the verilog files ncvhdl -f ncvhdl.options # Compile the vhdl files

There are two points, i cant understand:

  1. fprint.vhd + fprint_body.vhd were compiled, but put to the WORK, however, i want it in FPRINT
  2. $XILINX/verilog/src/simprims/*.v cant be compiled, an error: ncvlog:
*E,BADFIL: invalid file: /design/software/XILINX/ISE/8.2i-SP1/verilog/src/simprims (not a regular file)

Thanks for your answer, :)

Regard, Cheng

Reply to
uvbaz
Loading thread data ...

No one interest in this problem? The formulationg not clearly?

Reply to
uvbaz

I have problems already. If you want an answer, ask a question. If you want to print text from your simulation, try the REPORT statement.

-- Mike Treseler

Reply to
Mike Treseler

Hi, Mike,

I'm sorry if i havent clearly describt the question: The files 1 to 4 are the configuration files, file 5 is the script, run file. My question are:

  1. I want to compile "fprint.vhd + fprint_body.vhd" in FPRINT, but it didn't. Why?
  2. "$XILINX/verilog/src/simprims/*.v" not recognized, why?

Thanks for your patient, Mike.

Regards, Cheng

Mike Treseler schrieb:

Reply to
uvbaz

Until you learn modelsim, compile everything into the default library "work".

Maybe it is a verilog file and the script is running vcom.

-- Mike Treseler

Reply to
Mike Treseler

file, and running the tool with the -f option to feed it in. I notice that you have //comments in your script file. I suspect that the /* in your pathname is being interpreted as a start of a block comment in the script file. This would mean that the path stops at simprims, followed by the start of a block comment /*.v. So you are trying to compile simprims, which is a directory. Note that the path printed by your error message ends at simprims.

There is probably some way to escape the * character to prevent this from happening, but I don't know what it is.

Reply to
sharp

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.