comparison with integer

Try your question on comp.lang.verilog. In vhdl I would use an integer range or unsigned. Whatever XST is doing, I expect that it would match modelsim. I prefer trial-and-error simulation to synthesis.

-- Mike Treseler

Mike-

Thanks Mike.

The code above never makes equality, but I don't know how to fix it. Would you know what this means:

Q13. An unconstrained integer results in bad quality. A13. This is a known limitation in XST. Support for this is planned for ISE 9.1i.

This is on page:

but I can't find any other Xilinx reference to it.

-Jeff