comparing Xilinx XC3S500E-4CPG132C vs Altera Cyclone IV FPGA (EP4CE22F17C6N) apples to apples.

the xilinx says it has 500,000 gates,

the altera says it has

22,320 Logic elements (LEs) 594 Embedded memory (Kbits) 66 Embedded 18 x 18 multipliers 4 General-purpose PLLs

so are these two fpga's comparable in size/ computing power/ ability to support the same VHDL or what?

Reply to
jleslie48
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Hi, The comparision of two types of FPGAs is not simple. Your statement about the Xilinx device is oversimplified. It is useful for comparisions of Xilinx devices of the same family, but nothing beyond that. Also this method has already been kind of "dropped" for more recent device families.

For all Xilinx devices there are also informations available that are more comparable to the informations you have listed for the altera device. e.g for the S3E-500: 1,164 CLBs = 4,656 Slices of 2 LUts 2FFs and some Carry logic 360K BRAM 20 Multipliers 4 DCMs

And for the othere informations consult the datasheets of both devices. VHDL is always the same, but the tools may have special support, that can cause incompatibilities. So the correct usage of some HDL is more or less depending on the skills of the engineer that is working with it.

Have a nice synthesis Eilert

Reply to
backhus

As already said the comparision is not simple but a starting point is a comparision of LUTs and flipflops. Even then you need to take account of variation in LUTs e.g. Spartan-6 has a 6 ip LUT which might be comparible to 2 x 4 ip LUT in a Spartan-3.

If you design needs a lot of ram e.g. for video or multipliers for DSP these are also things to look at.

Ultimately if your design, or part of it, is available you can always do a trial build. Both Xilinx and Altera have free versions of their tools which you could a trial even if the size of device you are interested in isn't supported in those versions just try in for a smaller one and get a logic size out of that.

John Adair Enterpo> the xilinx says it has 500,000 gates,

Reply to
John Adair

The XC3S500E (this is an older family) is about 50% of the resources as a EPC4CE22

XC3S500E EP4CE22 LE - 10,476 22,320 Memory - 360K 594K Mult-18x18 - 20 66 PLL/DCM - 4 4 Max IO - 232 150

The XC3S1200E (same family) is closer in resources and the next size up is about 50% larger:

XC3S1200E EP4CE22 LE - 19,512 22,320 Memory - 504K 594K Mult-18x18 - 28 66 PLL/DCM - 4 4 Max IO - 304 150

The same modern family from Xilinx as an EPC4CE22 is the Spartan-6 line: XC6S25 EP4CE22 LE - 24,051 22,320 Memory - 936K 594K Mult-18x18 - 38 66 PLL/DCM - 6 4 Max IO - 266 150

Ed McGettigan

-- Xilinx Inc.

Reply to
Ed McGettigan

Thanks for all the thoughts on this. I realize these things are still in their infancy, but the "computing power" in general terms should be comparable between different brands of FPGA's. I'm not looking for accuracy to 4 decimal places, but just a ballpark expectation. Ed's values seem to give good apples to apples values for comparision.

My first project with fpga went well enough until I tried to fit it onto a cpld chip only to find that the CPLD chip was 1/1000th the size of the spartan 3E I was using as a development target. When something is 3 orders of magnitude different, I should be able to tell reasonably easy.

So my walkaway from this thread is: in the future, a better "marker" for size is LE's instead of gates.

Reply to
jleslie48

Hi, and again you are about to make the same mistake as before.

Don't try to nail down the capabilities of such complex devices as FPGAs to a single number.

And don't forget to include the skills of the engineer(s) in your calculation.

Have a nice synthesis Eilert

Reply to
backhus

Certainly better, but in no way sufficient :)

That'd be like choosing a micro based on DMIPS with no regard for peripherals, IO count, on-chip memory (volatile and non-volatile)... It's just that when you're already used to choosing micros - for your first-pass shortlisting - you already trade all those off without thinking conciously about it.

Cheers, Martin

--
martin.j.thompson@trw.com 
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.co.uk/capabilities/39-electronic-hardware
Reply to
Martin Thompson

*Meaningful* "apples to apples" comparison of this type is impossible. Not = only across vendors, but also across different architectures from the same = vendor, where the "units" are supposedly the same.

You start out by considering gates, LEs and slices, which get you nowhere u= seful -- it really doesn't give you any good indication on how efficient yo= ur design is going to be mapped into the architecture, for example. (Counti= ng FFs and LUTs isn't helpful because there are restrictions on how they ar= e used due to bundling). Then the next thing is to try targeting your desig= n for different architectures. But are the results meaningful? Did you lose= performance due to a generic design? Did you use the same software? Same v= ersion? Same settings? Did you correctly convert architecture specific prim= itives (BRAMs, DSPs, etc.) across architectures? Does your code happen to b= e optimized for one architecture but not the other? It's difficult for me t= o imagine hearing satisfactory answers to some of these questions.

So what *can* you do? Look at the context of your application: your needs, = your experience, and your budget. Which architecture has hard cores for wha= t you are trying to build? Which vendor supplies readily available soft cor= es ("IP") that you need? Do you have more experience with one of the vendor= s? Did one of the vendors give you a better deal? Which device has a cheap = dev kit you could use? Are free tools available for your target device? If = you're a student, which vendor is your University using for their classes? = And so on...

Once you answer those, that initial comparison wouldn't seem so important.

Reply to
saardrimer

In the olden days (before BRAM and embedded multipliers) there was some use for this number, though very little. A little less useful than MIPS (Meaningless Indicator of Processor Speed) is of serial CPU performance.

But now it includes the logic in BRAMs and multipliers, and anything else that they add on. Often your design doesn't use these additional resources in the exact proportion that they are supplied, and so the extras go to waste. (Like CPU cycles while waiting for I/O.)

This allows you to separately determine the logic, block memory, and block multplier resources. You alse need to know the size of an LE to compare with anything other than another device in the same family.

Is a 200MHz Pentium faster than a 250MHz PowerPC 620?

--glen

Reply to
glen herrmannsfeldt

hi, here is the answer for your question. this reply doesnot support pictures to post so please go to the below link to view the differences between cyclone IV,spartan 3e(xc3s500e),spartan

3e(xc3s1600e),virtex-5(top1).

formatting link

i'll prefer de0-nano board will be the best board among these all,it is portable,handy,smart,and featured in many ways among all those,

thanks subhrajit

Reply to
mitra.subhrajit007

hi, here is the answer for your question. this reply doesnot support pictures to post so please go to the below link to view the differences between cyclone IV,spartan 3e(xc3s500e),spartan

3e(xc3s1600e),virtex-5(top1).

formatting link

i'll prefer de0-nano board will be the best board among these all,it is portable,handy,smart,and featured in many ways among all those,

thanks subhrajit

Reply to
mitra.subhrajit007

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