comparing between Xilinx and altera

I have a project that need about 300KLE, I want to choose a device between the Xilinx V7 and Altera Stratix5, please give some suggestions, in the low

-end devices,what is the key diffrence between spartan6 and Cyclone5,which have the better route pass percentage?And which have the better resource us eage?And which have the better power consumption?

Reply to
bjzhangwn
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Xilinx V7 and Altera Stratix5, please give some suggestions, in the low-end devices,what is the key diffrence between spartan6 and Cyclone5,which have the better route pass percentage?And which have the better resource useage?And which have the better power consumption?

It's been a while since the last X vs. A wars, here. But it seems you are asking two differenct questions. First for 300KLE and either Virtex7 or Stratix5. I assume that the Spartan6 vs Cyclone5 question is separate because I don't think they go up to 300KLE (I know for a fact that Spartan6 only goes to 150KLE). And now there are newer "low-priced" Artix parts from Xilinx if you wanted to look at 7-series for comparison with the latest Altera low-cost parts. Artix goes up to 200KLE (right now I think the only two sizes available are 100K and 200K). Artix can also do x4 PCIe if you need that. Spartan 6 LXT only has 1x endpoint blocks.

Not sure what you mean by "route pass percentage." If you're talking about the amount of logic you can stuff into a part before it becomes unroutable, then Xilinx parts are pretty good. You usually get to a point where it's too hard to meet timing (due to slice packing and other placement constraints) before you get an unroutable design. I generally consider about 70% LUT usage to be "full" from this perspective. No experience on altera parts.

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Gabor
Reply to
GaborSzakacs

I think this is one of those questions like, "how long is a piece of string"? The utilization percentage depends entirely on your design. I did a design on a Lattice part a while back and when the customer wanted an upgrade I warned that it would likely push the utilization up to 80% or more which might make it hard to route and meet timing. Sure enough, the project got to about 80%, but we had no problem at all with routing or timing. Certainly the tools are better than they were back when I almost did harakari working on a design update at over 90% utilization.

So I don't think there is a good answer to the question. But there is a not-so-bad solution. Unless you plan to instantiate vendor specific components, you should be able to write your code without making the decision about the vendor. When the design is done or nearly so, generate bit files on both tools and see which fits best. The most likely answer is, "it doesn't matter".

Power consumption can be measured very easily on most development boards. They are usually less than a weeks pay and sometimes less than a day's pay. Or you can ask the vendor...

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Rick
Reply to
rickman

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