Hi,
I am working on a study to copmpre the effiency of synthesied adders. I have built a ripple adder and a carry look ahead using VHDL for a Virtex FPGA. I know that the lookahead carry adder is much faster than the ripple carry adder but when I synthezied both fro a 16 bit adder i got only an improvement of 2ns using the lookahead carry adder.
For the lookahead adder i built a 1 bit adder which generates the P,G,Sum and Carry and than built the lookahead logic using standard techniques. The carry in was computed as :
C(i)