Comparing Adder synthesis techniques

Hi,

I am working on a study to copmpre the effiency of synthesied adders. I have built a ripple adder and a carry look ahead using VHDL for a Virtex FPGA. I know that the lookahead carry adder is much faster than the ripple carry adder but when I synthezied both fro a 16 bit adder i got only an improvement of 2ns using the lookahead carry adder.

For the lookahead adder i built a 1 bit adder which generates the P,G,Sum and Carry and than built the lookahead logic using standard techniques. The carry in was computed as :

C(i)

Reply to
Joseph
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If your ripple carry adder was just A

Reply to
David R Brooks

I expect that an unsigned or natural range adder just using '+' would work just as well. Synthesis is quite clever with the carries for most adder descriptions.

Maybe your expectations about synthesis were wrong. Have a look at the RTL viewer.

-- Mike Treseler

Reply to
Mike Treseler

Usually the lookahead adder has n bits of propagate and generate signals, not one. That's where the efficiencies come in. For bits 24-27, a sum of

4'h15 is a propagate and the generate out is immediately available to bits 28-31. The longest path is the decision to propagate plus the time for the first stage generate to pass through the chain of propagate signals.

If you do this one bit at a time rather than several, there isn't much of a time savings.

Where are you reading up on what a lookahead architecture brings with it in advantages and disadvantages?

- John_H

Reply to
John_H

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