combinatorical divide by 2 in FPGA

Hi Antti, One has to wonder .. why ? :)

You will have to fight/override the tools, as this is not-natural as far as they are concerned. I tried this a while ago - in my case, a latch in PLD foldback nodes, and the logic itself is not complex, but the tools take one look at the buried hold loops, and optimize them away ! -jg

Jim Granville schrieb:

why? I can answer this, I need the flip flop to toggle *BEFORE* FPGA configuration is completed, eg at the time when fabric clocked resources are not useable.

and yes it seems like kinda PITA thing todo.

Antti

Can't you delay startup of the rest of the circuit while starting the divider immediately after configuartion?

--
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
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Uwe Bonnes schrieb:

I want to quick start the STARTUP primitive without the use of external clocks. so I need 10 pulses at the time when GSR GTS are asserted and GWE is not released. this is maybe just a few config clokc pulses

*BEFORE* the FPGA actually starts to work. only wiring and combinatorical logic is activated. the divider is only need *until* done goes high, not any more after that.

Antti

Hi Antti, A while back I did something similar by instantiating LUT primitives. e.g.:-

component LUT4 generic ( INIT : bit_vector := X"0000"); port (O : out STD_ULOGIC; I0 : in STD_ULOGIC; I1 : in STD_ULOGIC; I2 : in STD_ULOGIC; I3 : in STD_ULOGIC); end component;

The tools weren't clever enough to look at the INIT number and attempt 'optimisation'. Good luck, Syms.

Sounds like you need a master/slave pair of latches (a DFF made out of gates). The only trouble would be convincing the tool to not optimize out or complain too harshly about the combinatorial loops.

Two SR Latches chained together. The S and R inputs are the normal and inverted signal from the other stage (inverted between one pair) and the clock acts as a 3rd input - normal on one SR Latch, inverted on the other - to each NAND gate to make the latch transparent or to allow the latch.

I'm thinking back to the old TI data book that mapped out all the simple TTL logic. Since you don't need asynchronous set/reset logic, you should need just the 4 LUTs.

LUT instantiation. But you already know that. A good excuse to revisit those Digital Logic 101 textbooks...

My memory is that Peter Alfke did this a while back, possibly in his search for the fastest frequency counter in the galaxy ;-) Check the archives.

Tim schrieb:

yeah, I know the LUT path, will have todo it that way

Antti

Two LUTS/FF. Only one LUT required per latch, one for master latch, one for slave, and . wiring, err routing, delays should be verified. I'd list the init values, but haven't had my coffee yet this morning. Just John

JustJohn schrieb:

hm, get your coffee and write it down :) and you get extra e-coffe from me.

the non-LUT version of the master slave thing did not yield anyuseful result. sounds interesting to have a FF out of 2LUT (if it work also..)

Antti

Antti,

It might be safer from a delay standpoint to use the slice flip-flops but using only the async R and S inputs, and tying the clock to ground. I'm not sure this will satisfy your need though, because that FF might be held reset during the part of start-up when you are intending to use it. Just thought I'd mention it as an alternative.

Ray Andraka schrieb:

Thanks, - a good suggestion but it seems not useable. the S-R trick doesnt work either :(

Antti

Ray Andraka schrieb:

uups - it may actually work, I had a test setup where I used SR flops but it also had someother things, and I did not build the divider out of SR flops, so I can retest the solution.

SRL16 based divider doesnt work for sure that I checked.

Antti

(Not recommended for critical applications!) Two 4-LUT divider, does not optimise away, sims ok too, max clock is route dependent, you probably want to add RLOCs to force the same slice for the LUTs, give Clock a chance to have close to identical delays to both LUTs, if Clock delays are different, make sure the Slave LUT is later. You can toss the Reset term and instantiate LUT3s instead of LUT4s.

Let us know if it works for you...

library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VComponents.all; entity Antti_FF is Port ( Clock : in STD_LOGIC; Reset : in STD_LOGIC; Div_2 : out STD_LOGIC); end Antti_FF; architecture Behavioral of Antti_FF is signal Master : std_logic; signal Slave : std_logic; begin Master_LUT: LUT4

-- Master LUT (First in the Master/Slave FF)

-- Holds Feedback when clock is high,

-- Passes Inverted Data when Clock is Low.

-- Reset available using 4-LUT, can be tied to 0

-- R=Reset D=Data C=Clock F=Feedback O=Output

-- R: 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0

-- C: 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0

-- D: 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0

-- F: 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0

-- O: 0 0 0 0 0 0 0 0 1 0 1 0 0 0 1 1 generic map ( INIT => x"00A3" ) port map ( O => Master, I0 => Master, I1 => Slave, I2 => Clock, I3 => Reset ); Slave_LUT: LUT4

-- Slave LUT inverts Clock sense,

-- Passes Data when Clock is High,

-- Passes Feedback when clock is low

-- R: 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0

-- C: 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0

-- D: 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0

-- F: 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0

-- O: 0 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 generic map ( INIT => x"00CA" ) port map ( O => Slave, I0 => Slave, I1 => Master, I2 => Clock, I3 => Reset ); Div_2

"JustJohn" schrieb im Newsbeitrag news: snipped-for-privacy@h48g2000cwc.googlegroups.com...

WAU, now I have a Flif flop with may name on it! thanks a lot John I will defenetly try it out!

Antti

You are very welcome, and thank you too. This is the first time since I've been doing FPGA design (XC2064) I've felt compelled to use a post-route timing sim, and it was a good exercise. The sim showed a

1.03 ns delay from clock rising edge to output at the Slave_LUT (smallest Spartan3, -5 speed), not too bad compared to the tcko of .6 ns for the regular FFs. Looks like lots of timing margin given a clock input of 100MHz, but still pay attention to the clock timing difference at the LUT inputs. The delta should be kept well below (Tilo+route_delay(master_out to slave_in)) and well below (Tilo +route_delay(slave_out to master_in) ).

There may be a small worry about this circuit on start-up, I'm not sure what the chances are it oscillates a little before settling down, depending on clock phase when the LUTs and routing go active, if that makes any sense (It's after midnight here, I'm going to bed, don't really feel like thinking about it). That's what I'm hoping to hear back from you, if you see any bad behavior.

Here's the LUT3 version, including RLOCs. The reset term was to make the simulation work...

p.s. The Antti_FF is a minor pun on the inversion in the master stage. Not sure if you, Syms, John_H, or some unknown engineer who's done this circuit in the past should get the credit, but I prefer the pun. ;o)

library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VComponents.all; entity Antti_FF is Port ( Clock : in STD_LOGIC; Div_2 : out STD_LOGIC ); end Antti_FF; architecture Behavioral of Antti_FF is signal Master : std_logic := '0'; signal Slave : std_logic := '0'; attribute rloc : string; attribute rloc of Master_LUT : label is "X0Y0"; attribute rloc of Slave_LUT : label is "X0Y0"; begin Master_LUT: LUT3

-- Master LUT (First in the Master/Slave FF)

-- Holds Feedback when clock is high,

-- Passes Inverted Data when Clock is Low.

-- D=Data C=Clock F=Feedback O=Output

-- C: 1 1 1 1 0 0 0 0

-- D: 1 1 0 0 1 1 0 0

-- F: 1 0 1 0 1 0 1 0

-- O: 1 0 1 0 0 0 1 1 generic map ( INIT => x"A3" ) port map ( O => Master, I0 => Master, I1 => Slave, I2 => Clock ); Slave_LUT: LUT3

-- Slave LUT inverts Clock sense,

-- Passes Data when Clock is High,

-- Passes Feedback when clock is low

-- C: 1 1 1 1 0 0 0 0

-- D: 1 1 0 0 1 1 0 0

-- F: 1 0 1 0 1 0 1 0

-- O: 1 1 0 0 1 0 1 0 generic map ( INIT => x"CA" ) port map ( O => Slave, I0 => Slave, I1 => Master, I2 => Clock ); Div_2