Coding style

Hi,

Does anyone happen to know what will the following (software) code will look like after going through a synthesis tool? I was told, back in the school, that never use *HDL as a software language and should have a block diagram or data path before coding. But it seams that more and more people trust the synthesis tool rather.

// Verilog version reg [5:0] offset; // input reg [15:0] we; // input reg [15:0] data_in[127:0]; // input

reg [7:0] data_out [63:0]; // output

wire [5:0] offset0; // internal logic wire [5:0] offset1; // internal logic ... wire [5:0] offset15; // internal logic

assign offset0 = offset; assign offset1 = offset + 1; ... assign offset15 = offset + 15;

always @ (posedge clk) begin if (reset) begin // initial code here ... end begin if (we[0]) data[offset0]

Reply to
<khtsoi
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Doesn't your synthesis tool show you the logic blocks used for your code after targeting the FPGA?

In our case at school, uscing a Cyclone II FPGA from Altera, Quartus II synthesis tool gives you a graphical output showing you exaclty how much logic, where and routing.

Cheers.

Reply to
Ivan Wagner

The ISE does have a graphical logic block output but it failed even when synthesizing the code in XST. The only result we have for this code is from dc_fpga on Unix platform. Since I use a pure CLI environment, I don't know if it will generate any graphical result. Any info about this is welcomed. Yes, I know I can go to FPGA editor for everything, but it too complicate.

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Regards,
Tsoi Kuen Hung (Brittle)
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Reply to
<khtsoi

Hi, your question(s) target a lot of different topics and some are more a matter of opinion than plain facts. Let's try to answer them piecewise.

Most likely not, since the two codes are not identical and have errors:

is not the same as

and data[...] in the if-statements is not declared anywhere.

That is basically right. Focus on "as a software language" ! Search this group for "think hardware" and from these posings you will see what's the difference. (After this have a look at your code again)

Nonetheless you can write synthezizable behavioral descriptions of your hardware, if you know how to.

Some just trust and fail, others understand what the tools are doing with the sources and succeed.

I hope so :-)

While I saw from the sources that you want to implement some barrelshifting thing I failed to understand to understand the shift control. It just looked strange, but may be ok for the desired purpose and just clumsy coded. Drawing a scetch of the circuit you are about to design will always be the first step, even if you are going to use a HDL because you need to understand the circuit and how it should work. Then, if you understand your prefered HDL, you can code it straight away. Of course you can use PERL to generate repeating HDL statements, but it may also be possible to use loops to achieve the same result with less HDL.

Well, that probably is the fault of your source, and not of the tools. As you stated above HDLs should never be used as a software language, and that's what you did. Use it as a Hardware Description Language for synthesis and everything will be fine. One of our students once had a similar problem with some code that was announced as "synthesizable". It failed on ISE due to memeory problems and it took Synopsys DC several days(!) to create an ultralarge circuit. After recoding the design from scratch (but still with lots of behavioral statements) we got a nice small and fast circuit.

I have done (small) barrel shifters before with XST and lots of other stuff and it works well. While there were problems with array-synthesis in the past (not supported by XST) you should think about using arrays anyway.

Both have advantages and disadvantages, depending on the problems you have. HDLs may speed up your design time, because the tool does all the optimisation etc. But if performance is your ultimate goal (e.g. for high volume products to reduce costs) then you may reach a point where you can't evade "handywork". Which approach works out best depends on too many factors. So there is no simple answer to that question.

That's just the point :-)

The question is: Who has set this trend, and who's going to follow it? For academic or research purposes where you have a single multi million gates FPGA to test you design ideas in hardware this might be right and useful. (Think of it as synthesizable simulation acceleration)

But product designs have different goals.

Now, think where the engenieering newbies come from... :-)

Have a nice synthesis Eilert

Reply to
backhus

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