CMOS capacitive loads, transition probabilities and FPGAs

Ken,

A commont confusion is what dissipates power?

When you charge a node, you waste power in the resistance of the charging transistor.

When you discharge a node, you then waste power in the resistance of the discharging transistors (both generate heat).

If both edges generate heat, then you have to count them both.

The energy stored in a capacitor is 1/2 CV^2, but don't let that confuse you: you have to put it in, and then take it out! The devices that do the work dissipate the power.

Aust> Hello folks,

Where logic devices quote a Power Dissapation capacitance ( most glue logic does ), they adjust the 'C' so you plug in F ( ie that's two edges ) The C is thus more a modeling value, to get the Power/Freq to Fit. Nailing F is also not simple, as decode glitches and runt pulses can cost power, and real power is a combinaton of Clock Tree, and D-Q loadings. Measure of a real operating device is always a good idea :)

-jg

This is a bit misleading and irrelevant. The fact that power is only dissipated in the resistance has nothing to do with the total amount of energy expended in charging and discharging a capacitor. Regardless of what value resistance, even if it is not constant, the energy drawn from the supply is the same as long as the capacitor is charged to the same voltage. The energy may be dissipated in the transistor or in the poly track or a metal track or the bond wire or the external pin or even in the wire from the power supply to the board. But add them all up and you will get the same value each time you charge a capacitor to a given voltage.

So the amount of power consumed is related to the frequency of transitions and the size of the capacitance. Whether you calculate it from the rate of the rising edges or both edges is not relevant, that just changes the constant that you use by a factor of 2. As the OP said, when you charge the cap from 0 volts to Vcc, half goes into the cap and half is wasted. But the total always comes from the PSU and is always the same amount.

You can't have a 0 to 1 transition without a 1 to 0 transition, so why is this even an issue?

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(snip of (1/2) C V**2 discussion)

The issue is where the factor of two goes.

As previously said, when charging half is dissipated, and half goes into the capacitor. When discharging the rest is dissipated.

For some designs it is easier to count total transitions than to count rising or falling transitions. Otherwise, yes, it doesn't matter as long as the 2 and 1/2 are in the right place.

-- glen

Hi chaps,

Many thanks for the replies.

(snip)

So, if 'a' is counting 0 to 1 only, then:

P = aCV^2F

is correct.

If 'a' is counting 0 to 1 and 1 to 0 then

P = 0.5aCV^2F

is correct.

Correct? :-)

In the 2nd case we use 0.5 because the 1 to 0 transitions dissipate energy already drawn on the 0 to 1 transitions and we do not want to count it twice?

I have seen the 2nd equation quoted often also with 'a' being referred to as the transition density at the node (which I assume means 0 to 1 and 1 to 0). I have also seen the 1st equation quoted with the same definition for 'a'. They can't both use the same definition for 'a' and be right....

Cheers,

Ken

They can if they adjust C :) If you are in a physics class, you have know C, ( and so 1 / 0/5 matters) but inside the devices, there are many C's and many drivers, so you choose an _effective_ C to match a point on the Power/Freq curve. If you want F to be edges, or F to be Clock that's up to you.

The above eqn gives a feel for the physics, but is not the whole story. In data sheets, you will see a series of Power Dissipation Capacitance [effective] values quoted, to give the best fit for operating conditions. [ and of course, none of this factors in device leakage ]

-jg

Ken wrote: (snip regarding energy dissipation in CMOS)

The 1/2 comes from the integral of V dV, which is 0.5*V**2, or, as you said earlier, half ends up in the capacitor and half in the resistor. Stored energy in a capacitor is always 0.5*C*V**2.

-- glen

I don't know of any chip power calculations that require you to come up with the constant yourself. If the chip vendor gives you a constant and tells you to multiply by 1/2 or multiply by 2 or to just use the constant as is, then where is the problem? I think the OP was just confused about the variations in the formulae. It is just a matter of how you figure the constant. Normally the constant is measured rather than calculated, so you just need to use the formulae that you are given with the constant.

--

Rick "rickman" Collins

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Hi Ken et al:

Just a couple more points on power equations. As some posters have indicated, the kCV^2f equations give you the right shape, and simple power models are tuned to make it work. One thing that works for the developers of power models is what goes up must come down -- the number of 0->1 and

1->0 transitions are equal. So if we can get one constant that represents the total switching current from supply to ground for a pair of transitions, we can then multiply that by the frequency of transition and the supply voltage to come up with a good stab at dynamic power over a set of transitions.

It is worth noting that there are many factors that go into the current drawn during switching. In addition to the charging & discharging of capacitance, you also have the crow-bar or short-circuit current of CMOS logic. This current will depend on whether you have a rising or falling edge due to different rise- and fall-delays (and input slew rates) which depends on the exact ratioing of the logic and upstream drivers. But again, if you measure the power over a rising + falling edge and average it to get power per transition, this will work out.

Provided the assumption that switching current is linear in activity holds, you can lump the short-circuit current in with the charge/discharge current. Really you're just making an equation P = kf -- there is no physical capacitance in the equation anymore. One ramification is that such a model for a driver + wire cannot be scaled with wirelength to obtain a power estimate for a different wire -- the short circuit component does not scale the same way as the capacitive component.

At some point this P = kf model breaks down since rapidly switching nodes may not fully charge/discharge caps (or equivalently hit full rail-to-rail swing) since there is not enough time to do so. So "k" values obtained at low switching rates will tend to be pessimistic at high frequencies -- but that's probably good enough. You can make things arbitrarily complicated by considering crazy things like as power draw increases so too does voltage droop, so dynamic power per transition can actually drop... but these effects are subtle and the reality is that the biggest source of power error is lack of good estimates of switching activity per node!

Another fun part of things is that there must be enough constants k for all the various resources and situations of interest. For example, the switching power of a gate can depend on the logic values seen at the various inputs (beyond just affecting whether the gate toggles). This "state-dependent" dynamic power is a detail that could be ignored by taking an average or representative case and hoping that no design repeatedly hits a corner case, or it can be modeled if it is deemed important.

As discussed in some postings, you usually do not care where power is burned provided it is burnt on-chip -- view the circuit as a black box and you get Power = Current Drawn * Voltage. But if you take terminated I/O standards as an example, there is some complication since current supplied by on-chip rails is partially dissipated off chip. If you are designing your power supply, you want to know the current. If you are designing your cooling solution, you want to know the on-chip power dissipation. If you are looking at your system thermal management, total power dissipation is what you want.

The bottom line is 1/2CV^2F just begins to scratch the surface of the wonderful world of power!

Regards,

Paul Leventis Altera Corp.

On the subject of variations and locations of 0.5 and 2 factors:

if we have

C as the node capacitance 'a' as the transition density (0 to 1 and 1 to 0) at the node then P = 0.5aCV^2F holds I believe?

Alternatively,

If 'a' is only counting "power consuming" 0 to 1 transitions then we have:

P = 0.5(a*2)CV^2F = aCV^2F

Correct?

Or is the factor of 2/0.5 worked into the C constant?

Ken

Rick,

Thanks for clearing that up. Good way to think about it. The 1/2CV^2 comment was confusing, I agree.

Aust> Aust>

Actually, I don't recall ever seeing a formula with the "a" coefficient. I have always just worked with a variable F to account for differences in the number of transitions.

The energy required to move charge onto a capacitor is Q*V. As you move more charge onto the capacitor the voltage rises linearly with the amount of charge so that V = Q/C. The total amount of energy stored on the capacitor at any voltage is the integral of the V vs. Q curve which is Int(V dQ) = Int(C*V dV) = 0.5 * C * V^2. If the capacitor is charged fully from a constant voltage source via a resistor, the curve to integrate is just a constant Vcc vs. Q which gives you an integral of C

• Vcc^2. If you want a power level you must multiply by F, the rate of charging the cap (not discharging since that consumes no extra power, it just dissapates the power stored in the cap). That gives you P = F*C*V^2. So the whole "where did the 0.5 come from" question has no answer. There is *no* 0.5 inherent in the equation. If someone wants to change it by counting *both* the positive and negative transitions, then you will have to multiply by 0.5 to compensate.

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Rick "rickman" Collins

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There is another factor of 2 to consider. If the clock is running at F, a FF can only toggle at F/2.

Is your F the clock frequency or the frequency of a FF toggling on each clock tick? (bottom bit of a counter)

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Hi Rick,

I guess the 'a' is just a suitable modifer for F so that readily available numbers can just be plugged in (i.e. fmax for FPGA).

One example of many I have found that define 'a' is at:

(see section 3.2)

Also, "Minimizing Power Consumption in Digital CMOS Circuits" by Chandrakasan seems be often referenced and defines such a term (alpha, on page 2, right-hand column).

Ok, in that case, my 1st option holds?

'a' is the transition density (0 to 1 and 1 to 0) at the node F is the clock freq C is the node capacitance V is supply voltage then P = 0.5aCV^2F

where the 0.5 is modifying 'a' since 'a' is counting all transitions (0 to 1 and 1 to 0) instead of just the power consuming ones (0 to 1)?

Cheers,

Ken

Hi Hal,

(snip)

I think that this must be taken care of in the 'a' term so that the clock freq can just be plugged in to F.

In

they actually modify the C term with transition probability and call it "effective capacitance"!

One example they give for the probability of a 0 to 1 transition for a 2 input NOR gates comes out to 3/16 which is multiplied with C but is effectively the 'a' term we have been discussing I believe.

Ken