CML output swing for V5

the Common mode voltage and differential voltage from the Xilinx FPGA?

Here is a simplified description:

Each output pin has a fixed resistor of 50 Ohm to its supply voltage Vcc. There is also a ~ 10 mA constant-current pull-down generator, common to the two differential pins. Each pin has a transistor that connects or disconnects the constant pull-down current to the pin.

That means, the output voltage per pin swings between Vcc and Vcc minus about 500 mV, which thus creates a differential output voltage of about 1000 mV peak to peak, with a common mode voltage of about Vcc minus 250 mV.

Peter Alfke

the Common mode voltage and differential voltage from the Xilinx FPGA?

the Common mode voltage and differential voltage from the Xilinx FPGA?

This is my third attempt to post the answer: Each pin has a 50 Ohm resistor to its Vcc Each pin has a transistor connecting the pin to a 10 mA constant- current pull-down. The two complementary pins share a common constant current, and the two transistors are alternatingly driven on or off. Result: 500 mV swing per pin, 1000 mV peak to peak for the pair Common mode voltage is (Vcc minus 250 mV) Peter Alfke, from home

Thank you for providing this information.

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