A have 3 clocks(clk1, clk2, clk3) and I need to make a switch between these 3 clocks. My output master clock is CLK. I have a parameter, let's say 1000. I need to make first 200 pulses of CLK with clk1, then 600 pulses of CLK with clk2, then last 200 pulses of CLK with clk3. How can I implement this in verilog?? Thanks,
- posted
19 years ago