Clocking ZBT RAM via DCM on ML40x board

Hello Tomasz,

Here is part of my UCF file

NET sram_clk_pin LOC = AF7; NET sram_clk_pin IOSTANDARD = LVCMOS33; NET sram_clk_pin DRIVE = 16; NET sram_clk_pin SLEW = FAST; NET sram_clk_fb LOC = AD17; NET sram_clk_fb IOSTANDARD = LVCMOS33;

As you can see, I am driving AF7 and receiving feedback on AD17.

The problem might be on the schematic that both signals are labeled with the same name, they have to, since they share common copper. I recall that the designer put a comment on AD17 indicating that it is feedback although I didn't trace the paths to see if there would be a difference in switching the two lines.

I am also using, per Xilinx instruction, two DCMs, one for the internal workings and one to drive the external clock pin.

I am using 100 MHz, clk90, with an initial tap delay of 55 or about 2.1ns. Not too sure about my reset circuitry. Hope you read VHDL:

sbuf_external_clock_pin_dcm: sram_dcm port map ( clkfb_in => sbuf_domain_m_clk_fb, psclk_in => sbuf_domain_d_psclk, psen_in => sbuf_domain_d_psen, psincdec_in => sbuf_domain_d_psinc, clkin_in => sbuf_domain_m_clk, rst_in => sbuf_domain_m_reset_raw, clk0_out => open, -- 170 taps clk90_out => sbuf_domain_m_clk_pin, -- 22 taps to 74 taps clk180_out => open, -- 160 taps clk270_out => open, -- 100 taps to 120 taps locked_out => sbuf_domain_m_lock, psdone_out => sbuf_domain_d_psdone );

-- Set the following: -- CLKIN FREQ 100 MHz -- PHASE DELAY VARIABLE_POSITIVE 55 taps -- CLKIN EXTERNAL -- Feedback External Single

sbuf_domain_m_reset_delay_SRL16 : SRL16 generic map ( INIT => X"0000") port map ( Q => sbuf_domain_m_lock_delayed, A0 => '1', -- 16 clock delays A1 => '1', A2 => '1', A3 => '1', CLK => sbuf_domain_m_clk, D => sbuf_domain_m_lock );

sbuf_domain_m_reset_process: process(sbuf_domain_m_clk) begin if( sbuf_domain_m_clk'event and sbuf_domain_m_clk='1') then sbuf_domain_m_reset Hello,

Hello Brad,

Thanks for your reply. It seems I was doing everything similiarly with one exception though that I didn't enter the IOSTANDARD and DRIVE parameters in my UCF file. Without this, there was no signal present on AD17. Actually, leaving only DRIVE = 16 for the clock output does its job (the signal is feeded back where it should be) and could end the topic, however I've got yet another question. When I set the IO standard for sram_clk_fb, as in your example, I cannot get through the PAR stage as it terminates with errors:

ERROR:Place:311 - The IOB ZBTRAM_CLKFB_PIN is locked to site IOB_X1Y51 in bank 4. This violates the SelectIO banking ERROR:Place:207 - Due to SelectIO banking constraints, the IOBs in your design cannot be automatically placed.

This confuses me a lot since it's not the first time I've got this message (it happens quite frequently when I set IO standards manually). There are no other specific constraints in my design that could mess with those settings (or at least I think there aren't), I just make some simple pin assignments.

Regards, Tomasz Dziecielewski

This is part of the console output when I run the FPGA editor. Use a wide screen to view it. Why don't you look to see if it matches what you get?

Bank 4 has 16 pads, 2 (12%) are utilized. Name IO Select Std Vref Vcco Pad Pin ---- -- ---------- ------ ------ ------ ------ sys_clk_in I LVCMOS33 NR 3.30 IOB_X1Y55 AE14 None L sram_clk_fb I LVCMOS33 NR 3.30 IOB_X1Y51 AD17 None Vr-Term L

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