Hello boys,
I have got a small problem with my finite state machine which I have written in VHDL recently. I tried to create "intelligent" counter triggered by clock with frequency 2 Hz.
This counter is built in one state of FSM and is started by pushing a button on DE2 board.
Firstly, whole system is in IDLE state and if I push this button, state is changed to COUNTING and counter begin to be incremented and his current value is shown on LED display. After it reach value of modulo, the state COUNTING is left back to IDLE and the counter is set up to zero.
My problem is that the counter doesn´t work correctly - the counting value was too great. So I tried to solve it with this construction: if (clk_tick´event and clk_tick = 1) then.... , there are some errors by synthesis:
Error (10822): HDL error at Citac_FSM.vhd(57): couldn't implement registers for assignments on this clock edge
Error (10821): HDL error at Citac_FSM.vhd(62): can't infer register for "AUTOMAT:flg" because its behavior does not match any supported register model
Please, does somebody have an idea to solve it? And what is it correct way to write clock triggered FSM with two (or more) clock sources?
----------------------------------------------------------------------------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_unsigned.all;
-- Entita ENTITY Counter_FSM IS GENERIC ( REGSIZE : integer := 8; -- range of counter MODULO : natural := 50 -- modulo value ); PORT ( CLK : IN STD_LOGIC; -- puls 50 MHz CLK_tick : IN STD_LOGIC; -- puls 2 Hz RESET : IN STD_LOGIC; -- reset READY : OUT STD_LOGIC; -- counter is ready to start START_C : IN STD_LOGIC; -- start of counting DOUT : OUT STD_LOGIC_VECTOR(REGSIZE - 1 downto 0) -- output ); END Counter_FSM;
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