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Clock Synchronization of PC and FPGA

Hi Fellow, I want to send data to FPGA and store in register in FPGA sequentially. In my design it is required to take 12 input from the data bus in 12 different clock pluse one by one then I have to start processing data in FPGA and then the result after performing calculations is to be taking out of FPGA. The problem which I am facing is syncronization of clock. B/C I am downloading data using C code. In FPGA I have defined 100 MHz clock frqeuency and my processor is working on 2 GHz. SO if I have to send

12 data signals to FPGA then it will be taking input much slowly as compared to PC speed. And in my design Clock cycle is important because I am using clock cycle count's to do different things. Could any body please tell me how to synchronize the PC and FPGA internal clock. Do I need to use SLEEP command in C program to do that . And one thing more that C instruction also uses more then one clock cycle to perform particular task.

Any help in this regards would be appreciated.

Regards

Isaac

Reply to
Isaac
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How are you connecting your FPGA to your PC ?

Do you use any Development Kit ? Which?

Is your FPGA in a PCI board, directly accesing the PCI bus from your PC?

Are you using the serial interface to communicate with your FPGA?

As you can see, there are a lot of open questions to start solving your issues. However, I am nearly sure that you have no easy way of synchronizing the two clocks (unless you clock your FPGA with the same clock that clocks your CPU...), so will have to go to handshake mechanisms to transfer data from one to the other.

Give more info out, we'll put some answers out

TechCon.

Reply to
Technology Consultant

Hi Isaac !

I guess the best thing is to use a kind of "elastic buffer" working with different clock speeds as "asynchronous FIFOs". This will synchronize the data to your FPGA clock.

Just write to this FIFO with the maximum clocking speed you can reach by your interface (don't forget to think about handshaking) - maybe an implementation as FSM is usefull. For reading use a different clock. This read clock will be the same as you use it in your FPGA design.

Guess, you can find some nice hints at the Xilinx website how to build up a circuit like this.

Greets, Peter

Reply to
Peter Rauschert

I am fine . Thankyou .

I am using Xilinx ISE 5.2 i and Aldec Inc Software .

I am using HW2000 Inc .. PCI FPGA Development Board. Having four XCV600 xilinx chip with packaging HQ240.

I am using API function to Communicate with the Board. The Bus width is 32 bit and I have 36 bits input to FPGA. Thats why I want to send and store data sequentially in chunk of 3 bits or I could send 18 bits at a time in two clock cycle . As you said I might have to look for handshake mechanism and I have to do something like Interreput Request. If you have any idea then please tell me .

Waiting for response.

Rgds

Isaac.

Reply to
Isaac

I am glad [that] you are fine.

I could not find any documentation about the board you are using. Would you EMail some of it?

Regards,

TechCon.

Reply to
Technology Consultant

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