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CLOCK_SIGNAL constraint/XST?

Anyone had any luck with this constraint?

I can apply it in VHDL, and XST reports that it has seen and set the constraint:

Set property "CLOCK_SIGNAL = yes" for signal in unit .

However, further down in the logfile, it reports that the clock signal is generated by combinatorial logic, and it can't identify the primary clock signal. It then suggests using a CLOCK_SIGNAL constraint.

This clock is produced by combinatorial logic, and the output of the logic drives a BUFG. I've tried applying the VHDL attribute to both the input and the output of the BUFG, with the same results.

Thanks -

Evan

Reply to
Evan Lavelle
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You need to set this constraint when XST can't trace all clock signal in your design.

You have to identify all your clocks ports at the top level of you

design. Compare them with XST Clock information synthesis result This list reports the automatically identified clock nets, bu probably XST has missed one in your design. If so, set the attribute at the very top of your design, targeting the input clock signal tha was'nt present in the XST Clock information report

Good luck

/rock

Reply to
rocky

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